Volume 4, Number 9 -- March 4, 2008

IBM Launches 64-Way z10 Enterprise Class Mainframe Behemoth

Published: March 4, 2008

by Timothy Prickett Morgan

Ever since IBM put Star-class 64-bit PowerPC processors into its RISC-based RS/6000 and AS/400 lines in 1997 and scaled them up to a dozen processors in a single system image, you could argue that CMOS-based mainframes have taken a backseat to Big Blue's RISC machines in terms of raw performance. With the advent of dual-core Power4 servers in late 2001, the disparity only got worse as IBM broke through the gigahertz barrier, leaving mainframes in the dust. Last week, with the launch of the System z10 Enterprise Class mainframe, the mainframe is as close to parity with big Unix and proprietary RISC machines as it has been in a long, long time.

As you might imagine, IBM was keen on trying to position the z10 mainframe as part of a much larger set of initiatives and also to push this new server as a "quantum leap" in technology. This is what all of the top execs at all of the major IT companies do, of course. But the fact remains that this is a new and interesting piece of iron, with very sophisticated capabilities, and it is an evolutionary product, not a revolutionary one--much as the prior zSeries, System/390, System/370, and System/360 mainframes have been for the past four decades. (You could argue, quite correctly, that the System/360 was indeed a revolutionary product. I would.) First and foremost, and most importantly for IBM's hardware and related systems software businesses, this is and will always be a hardware announcement. Why system companies are embarrassed to say this is a bit mystifying.

Many of the details of the quad-core z6 processor were divulged in Big Iron back in October, but last week IBM put a little more meat on the bones. The z6 processor is running at a top speed of 4.4 GHz and is rated at 920 MIPS, according to Steve Mills, senior vice president and the executive in charge of IBM's Software Group who hosted the z10 launch in New York. (Jim Stallings, who is general manager of the Enterprise Systems division that is responsible for mainframe development and marketing was in Mumbai for a launch there, and Bill Zeitler, the senior vice president on charge of IBM's Systems and Technology Group, was hosting the Tokyo launch event.) This is considerably more oomph than the dual-core 1.7 GHz processors used in IBM's System z9 machines--about 600 MIPS, according to who you ask. The z9 engines were launched in 2005 and kept mainframe sales humming along until two quarters ago or so, when it became clear to customers that IBM had new mainframes in the works and business slowed down. (Difficulties in the financial services markets in the second half of 2007 didn't help mainframe sales much, either.) IBM's documents for the z10 say that the fastest z6 core is expected to deliver 62 percent more performance than the fastest z9 core, which had a much lower clock speed. (That would seem to suggest that the 1.7 GHz z9 processor core running full out should have been rated at 568 MIPS, which is lower than the numbers a lot of people have been throwing around for three years.)

The System z10 Enterprise Class.

That extra clock speed is important since the 4.4 GHz clocks IBM can now deliver in the z10 give it an edge over the 3 GHz or so clock speeds of X64 alternatives and the 1.6 GHz to 1.8 GHz clock speeds of the Itanium and UltraSparc-IV+ processors used by Hewlett-Packard and Sun Microsystems in their big iron Unix boxes. Plenty of workloads out there--such as Java applications and Web 2.0-style interpreted languages like PHP--are sensitive to the speed of the processors. Such applications also like L1 and L2 cache memory, and the z6 has these as well. Each core on the quad-core z6 chip has 64 KB instruction and 128 KB data L1 caches, plus 3 MB of L2 cache per core. (This is a lot more cache than the z9 processors had, and that extra memory is a key to the performance increases that come with the z6 chip.)

As has been the case with mainframe processors for years, the z6 chip will have data compression and cryptographic functions on the chip, and will include the new decimal floating point units that made their debut in the Power6 RISC processors that were announced last summer for the System p and System i lines. (Decimal units do so-called "money math" natively, not with a software overlay on existing integer math units in the chip.) Each core on the z6 chip has a binary/hexadecimal floating point, fixed point, and decimal floating point unit. There are two compression and cryptographic accelerators on the chip, shared by a pair of processor cores. The future z6 chip implements the IBM mainframe instruction set in 24-bit (System/360), 31-bit (370/XA), and 64-bit (z/Architecture) modes. As I explained last fall, the z6 is not just a reworked Power6 chip, as some people have mistakenly reported. The z6 chip has 894 mainframe CISC instructions (with 668 of them implemented in hardware), and supports PR/SM logical partitioning and z/VM instances with assistance from the chip. Incidentally, the pipeline in the z6 cores has been completely redesigned and streamlined to allow IBM to crank up the clock speeds on the unit to 4.4 GHz. (IBM also reworked the Power6 pipeline so it could push clock speeds up to 4.7 GHz, and it similarly got only a 50 percent in performance compared to 2 GHz or so Power5+ cores when it did so.) IBM says that the z6 processor has more than 50 new instructions to the z/Architecture to improve the efficiency of code that has already been compiled on prior mainframes.

There are five different models in the z10 EC lineup, which have been given the machine type 2097 in the IBM catalog. IBM is telling customers that in an SMP configuration, which gangs up processors into a single system image, a z10 running traditional mainframe workloads--of the COBOL-CICS transactions against IMS and DB2 database variety--will see about 50 percent more performance from a z10 machine over a z9 box with the same number of processors, and on non-traditional workloads--Linux virtual machines, Java applications, and such--customers could see performance as high as twice that of the z9 boxes. (Clearly, the clocks and cache do not help COBOL-CICS apps as much as it does other workloads.) The top-end 64-way z10 EC also has about 70 percent more aggregate MIPS than a top-end 54-way z9 EC server, which was rated at 17,800 MIPS. (A lot of computing is used up by SMP clustering inside the machine, as is the case in every server that has more than one processor.) That puts the 64-way z10 EC at around 30,000 usable MIPS for big, big mainframe jobs.

Given the nature of the kinds of jobs IBM runs on its big iron--whether it is System z, System i, or System p--you can see now why IBM has decided to get clocks as high as possible and not try to cram as many cores as possible onto a single chip. With the z6 chip, IBM has the best of both worlds--a real quad-core processor, no cheating by putting two dual-core chips side by side and sharing memory and I/O buses, and the fastest clock speeds in the market aside from its 4.7 GHz Power6 processors. This should make the batch jobs hum at Global 2000 companies. That's for sure. And it makes it all that more likely that Java, PHP, and other workloads can be moved to mainframes among those shops that already like mainframes.

There are five models in the z10 EC family of machines, and like prior mainframe designs and Power server designs, IBM is using book-style system boards that are then glued together to expand the processor, memory, and I/O capacity of the server. Both the z9 and z10 machines had five models, and both were based on four-book server designs. The z10 book has a total of 17 processing units (PUs), except for the high-end box, the 2097-E64, which has 20 PUs. Not all of these PUs can be dedicated to running z/OS or Linux; some can be configured as zIIP or zAAP co-processors, as system assist processors (SAPs, for running I/O), or spare SAPs. Each book has a maximum of 384 GB of main memory, but 16 GB of this is offset for use as a hardware system area (HSA) to improve the reliability of the memory subsystems. IBM is also using 12x InfiniBand links rated at 6 GB/sec compared to the Self Time Interconnect (STI) links used for I/O in the z9 mainframes, which were rated at 2.7 GB/sec. The z10 machines link the books together through their L2 caches in a star topology, which is meant to be more efficient compared to the ring topology used on the z9 machines (and on Power-based machines as well). IBM will eventually offer InfiniBand-based Coupling Facilities for the z10 machine to create Parallel Sysplex clusters, but these will not be ready until some time in the second quarter of this year.

Here's how the new z10 machines stack up:

Total Max Min Main Max Main Max zIIPs or Max Standard Standard InfiniBand
Model Books PUs CPs Memory Memory IFLs zAAPs ICFs SAPs Spares Links
E12 1 12 12 16 GB 352 GB 12 6 12 3 2 16
E26 2 26 26 16 GB 752 GB 26 13 16 6 2 32
E40 3 51 40 16 GB 1136 GB 40 20 16 9 2 40
E56 4 68 56 16 GB 1520 GB 56 28 16 10 2 48
E64 4 77 64 16 GB 1520 GB 64 32 16 11 2 48

All five z10 EC machines are available beginning February 26, and upgrades from zSeries z990 and System z9 servers are also available as of last week. Upgrade features within the System z10 machines--adding a processor book--will not be available until May 26, and model conversions within the z10 line will also not be available until then. The InfiniBand coupling links will be available some time in the second quarter, but the InfiniBand links to peripheral drawers and adapter cages are available now. InfiniBand coupling links will also be available as an option on System z9 EC and BC servers as well.

As for operating systems, you are going to have to be on some recent software to use the z10 iron. Specifically, z/OS V1.7, V1.8, or V1.9 with appropriate patches is required on the z/OS front, and it is only available in 64-bit z/Architecture mode. Novell's SUSE Linux Enterprise Server 9 and 10 and Red Hat's Enterprise Linux 4 and 5 are supported in 64-bit mode as well, and so is IBM's z/VM V5.2 and V5.3 and z/VSE V4.1 and z/TPF V1.1. TPF V4.1 and z/VSE V3.1 run in 31-bit ESA mode on the boxes.

IBM did not, as you might imagine, announce list prices for these new z10 EC boxes, but Karl Freund, vice president of marketing for the System z line (who used to have the same job in the System p line) said that the entry configuration of the z10 EC starts at around $1 million, not including software; he didn't tell me I was crazy when I suggested that a fully loaded z10 EC with 64 cores activated for processing, lots of main memory, and other required hardware would cost tens of millions of dollars. Even at $1,000 per MIPS, it works out to $30 million, and at $1,500 per MIPS, that's $45 million.

That's good business, if you can get it. Time will tell if IBM can, and based on its relative success with the z990 and z9 machines, there's a good chance that mainframe sales will perk up in the coming quarters, starting a whole new sales cycle. Over the coming weeks, IT Jungle will be pouring over the announcements, including the z/OS 1.10 preview, and talking to the IBM insiders to get a sense of how the z10 is being pitched and positioned to chase existing and new customers.


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