AMD's Chip Roadmaps: Beyond Barcelona

Published: August 27, 2007

by Timothy Prickett Morgan

Advanced Micro Devices is finally on the verge of delivering its quad-core "Barcelona" Rev F Opteron processors. AMD will be making the announcement in Silicon Valley on September 10, bringing its workstation and server processors more in line in terms of performance with Intel's quad-core Xeon family of processors. But what happens next? Intel is not exactly a sitting target like it was a few years ago. AMD is going to have to get its Opteron roadmap in order and hit targets to maintain, much less expand, its share of the profitable market for high-end X64 processors.

The ramping up of clock speeds for processors is pretty much over except for IBM's dual-core Power6 processors, which currently run at 4.7 GHz. IBM will probably will not push clock speeds much above 5 GHz in the Power7 generation, and is said to be moving to a multicore design, much as Intel and AMD have done with their respective X64 processors. Chip makers have decided to use the transistor shrinkage engendered by Moore's Law to cram more elements of a system onto a chip and to add more processor cores to each chip to boost the performance per socket. This approach, of course, assumes that workloads are parallelized to run on such machines, or that machine support multiple workloads. In a highly virtualized environment, as we seem to be moving toward in the data centers of the world, this is a pretty safe bet.

With the Barcelona Opterons, AMD is delivering the first true quad-core single chip to the market based on the X64 architecture; Intel's "Clovertown" chips are really two dual-core "Woodcrest" chips fitting into a single package and sharing a single CPU socket. AMD has been a purist when it comes to quad-core design for the Opterons and their Athlon variants, which will make Barcelona about six months late to market by AMD's own schedule and a year behind Intel's launch of Clovertown. AMD's approach might be technically elegant, but Intel got the money for the past year without much competitive pressure among customers who need the most threads and the most performance per socket.

The question now is, will AMD learn from this experience? The company will be getting Barcelona Opterons and their "Budapest" variants for the AM2 socket and bearing the Opteron 1000 and Athlon labels to market during the remainder of this year. Looking out further, AMD is working on a kicker to Barcelona called "Shanghai" and an eight-core chip based on a new core with a platform and chip code-name of "Sandtiger." The Sandtiger chip appears to be a real eight-core chip, not two quad-cores sharing a socket, and it is slated to be available in 2009. AMD might want to reconsider slapping two Barcelona chips into a single socket and getting a quasi eight-core to market to compete against Intel's future "Penryn" and "Nehalem" Xeon processors. The Nehalem chips will have eight cores with HyperThreading (giving it 16 threads per socket), on-chip memory controllers, and shared on-chip caches; these processors will blunt some of the key advantages of the Opteron architecture, if Intel gets them out the door on time.

According to Pat Patla, director of Opteron marketing at AMD, the Shanghai Rev F chip will have larger cache memories than the Barcelona chips, which is made possible by the shrink from 65 nanometer processors to 45 nanometer ones. AMD plans to get Shanghai into production in 2008; exactly when is unclear. But AMD has said that the Shanghai chip will have 512 KB of L2 cache memory per core, 6 MB of L3 cache (up from 2 MB in the Barcelona chips). Shanghai will also have other tweaks inside the core to improve performance, but Patla is not saying what right now and he is not talking about clock speeds, either. Shanghai will plug into the existing Rev F sockets and will stay within the same thermal envelope as the other Rev F chips; it will be available in standard, Special Edition (SE for short, and meaning higher clock speed and much hotter temperature), and Highly Efficient (HE, and meaning lower voltage and therefore lower heat for a given clock speed) variants. AMD is expecting third-party chipset makers to support the chip, much as nVidia and Broadcom do today.

As AMD plans to do with the Barcelona and Budapest chips, dual-core variants of the Shanghai processor will be available at lower prices for single-socket and dual-socket servers; presumably AMD will crank up the clock speeds on these chips, which have two cores deactivated, thereby boosting performance per thread while keeping within the same thermal envelope as the quad-core variant. On certain workloads, having a faster clock speed and the full L3 cache will make a bigger difference on performance than having more cores does.

Having made the jump to 45 nanometer processes in 2008 with the Shanghai Opterons, AMD will bring to market in 2009 the Sandtiger eight-core Opteron and the related socket and platform technology for that new family of chips. Patla says that AMD is not calling this new, larger socket that will debut with the Sandtiger chip the Rev G socket; he would not say what it will be called, but the odds are that everyone will end up calling it Rev G anyway. The socket will be physically larger because AMD is going to not only cram eight newly architected cores onto the Sandtiger chip, but also a lot of other things. And again, for all we know, Sandtiger will be a quasi eight-core chip, with two quad-core processors sitting side by side, sharing a socket.

Sandtiger chip will have more HyperTransport links between processors, memory, and I/O, and they will adhere to the HT 3.0 specification that was developed by the HyperTransport Consortium, and independent standards body that AMD gave control over the HyperTransport technology in an effort to make it more widely used in systems and workstations. With HT 2.0, which is used in the current Rev F Opterons and AM2 Athlons, the links run at a top speed of 1.4 GHz; HT 3.0 has links that can run at from 1.8 GHz up to 2.6 GHz, delivering a top-end 41.6 GB/sec of bandwidth, which is nearly twice the bandwidth. The Sandtiger chip will have four HT links per core, up from two on today's Opterons. (The extra HT links mean the chip needs more than the 1207 pins of the Rev F part, and therefore the socket is larger.)

Sandtiger will also support DDR3 main memory (and therefore a new memory controller will also be plunked on the chip) and a new technology called G3 Memory Extender (G3MX). This looks suspiciously like an external memory controller, but it appears that G3MX is a new way for the on-chip memory controller to interface with memory modules, allowing for greater memory capacities. The memory extender could also be used to create glueless four-socket and eight-socket servers, which would be interesting. The Sandtiger chips will also have support for virtualized I/O through a feature called the I/O Memory Management Unit, which is akin to Intel's VT for Directed I/O feature on its Xeon processors and often called VT-d. IOMMU will extend support of virtualization in the Opteron chips from the instruction set with the AMD-V instructions out to I/O functions.

Patla says that AMD is going to do its own chipsets for the Sandtiger Opterons for both servers and workstations, but will also work with third parties who want to make chipsets for them as well.

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