Intel Details Future 45 Nanometer Chip Plans from Beijing

Published: April 16, 2007

by Timothy Prickett Morgan

Rather than host its semi-annual Intel Developer Forum in its home stomping grounds of San Francisco, chip maker Intel is making the politically and economically significant move of hosting the spring IDF this week in Beijing, the capitol of China. Intel has 6,000 employees doing research and final testing and assembly at facilities in China, and has just inked a deal with the government to build Fab 68, a 300mm chip factory, in northern China. To say that China is important to Intel--and indeed, to all IT players--is an understatement.

Intel still does most of its primary research and development back in the United States, with some being done in Europe and the Middle East. And Intel has had mixed results for chip designs. The chip designers in India failed to unite the Itanium and Xeon chip lines through the "Whitefield" project and its Common Systems Interconnect, which was originally due this year. (Now, the CSI features are expected to appear in the future "Nehalem" processors two years from now or so.) The company's Israeli chip designers, who gave the company low-powered laptop processors and who paved the way for the Core architecture, should be credited for saving Intel's cookies in the chip business. Intel doesn't talk about the issue publicly, but as one of the largest creators of intellectual property and one of the most sophisticated manufacturers on the planet, Intel's knowledge is extremely valuable. With China being lax about enforcing patents and copyrights, any company with intellectual property has to be careful and walk a delicate balance to gain access to the world's largest population and a very large, often highly skilled, and low cost workforce. Hosting IDF in Beijing is a way of showing respect to China, which is the major reason Intel is doing it.

Of course, the IT industry is still largely focused in the Western economies, with San Francisco as its epicenter excepting some centers of gravity in New York, Texas, London, Paris, Tokyo, and several German cities. So Sean Maloney, Intel's chief sales and marketing officer, hosted a briefing today for analysts and journalists who cannot make the trip to Beijing to let them know what will be announced at the IDF event in Beijing by Intel's top techies. The announcements Intel is making have to do with its future 45 nanometer generations of chips, which will be based on a high k metal gate process and which will allow Intel to cram a lot more transistors on a piece of silicon and rev those transistors a little higher, too.

"We believe we have achieved a significant breakthrough with high k metal gate technology," explained Maloney. "This is arguably the biggest semiconductor development in the past forty years, and that is what our founder, Gordon Moore, has called it."

Intel has figured out a way to weave hafnium, a rare earth element that is also used in the control rods in nuclear reactors, into its chip designs. The resulting shrink to 45 nanometers using hafnium gates will allow Intel to double the number of transistors on a chip by late 2008 or early 2009, depending on the product line, while also reducing the amount of power used to switch transistors on and off by 30 percent, according to Maloney. Transistor switching speed will also be boosted by around 20 percent, and there will be a factor of 10 reduction in gate oxide leaking on the chips (hafnium oxide will control the flow of electrons). This latter bit is the big breakthrough, since electron leakage is an increasingly pesky problem as you shrink transistor geometries. IBM has also figured out how to include hafnium in its 45 nanometer designs.

Because we are so far away from the 45 nanometer chip deliveries from Intel or anyone else, the round of announcements coming out of Beijing are the typical code-name fiesta that happens every 18 months or so at Intel.

A few weeks ago, Intel divulged its future Penryn and Nehalem cores, the former being a slightly modified version of the current dual-core Core 2 and dual-core and quad-core Xeon 5100 and 5300 processors, but implemented in the high k/hafnium gate 45 nanometer process. Pat Gelsinger, general manager of Intel's Digital Enterprise Group, which creates the chips for desktops, laptops, and servers, will provide some more performance data on the Penryn chips. For desktop PCs, Gelsinger will show benchmark data comparing a pre-production quad-core Penryn chip running at 3.33 GHz using a 1.3 GHz front side bus and 12 MB of on-chip cache, which will best the "Clovertown" Core 2 Extreme QX6800 processor announced last week running at 2.93 GHz with an 8 MB cache and using a 1.07 GHz front side bus. The Penryn chip will deliver about 15 percent more performance on imaging applications and will be about 25 percent faster on 3D rendering; video games should run up to 40 percent faster, as will video encoding using encoders that are aware of the new SSE4 video instructions on the Penryn chips.

On the server and workstation front, Gelsinger's stats will show that bandwidth-intensive HPC workloads will be able to run about 45 percent faster, and servers running Java will see a 25 percent boost. (Presumably PHP and other interpreted languages will see a similar increase in performance.) These comparisons are based on a quad-core Penryn Xeon DP chip with a 1.6 GHz front side bus compared to the 2.66 GHz Clovertown Xeon X5355 with a 1.3 GHz bus.

Gelsinger also will remind the attendees in Beijing that it has a quad-core kicker to the dual-core "Tulsa" Xeon 7100 MP processor for four-socket and larger servers, the "Tigerton" Xeon 7300. The Tigerton chip and its related "Caneland" platform will come to market with 80 watt standard parts--the same thermal envelope as the Xeon 5100 and 5300 DPs--as well in a low-voltage part that runs at only 50 watts.

Because there always has to be some software angle at IDF, Sun Microsystems will be demonstrating Solaris 10 running on a "Woodcrest" Xeon 5100 server and, after some tweaks, making use of the dynamic power management features in the Xeon chips. Microsoft will also be on hand to demonstrate the future Windows Longhorn server and the Viridian virtual machine hypervisor that Microsoft created for it on a two-socket Clovertown box.

Intel also plans to talk a bit about its system on a chip (SoC) integrated designs, and another technology that is moving from the labs to product development to speed up processing for the HPC market. The "Tolapai" system on a chip will put an Intel X64 core and as yet unspecified components (probably memory controller, PCI ports, and networking ports) on a single chip, which is made possible by the 45 nanometer processes. All Intel will say about Tolapai is that the resulting SoC will be 45 percent smaller and use 20 percent less juice than the standard CPU-chipset design, which has four chips in total. The SoC products will also include something Intel is calling QuickAssist, which is a combination of hardware and microcode that will allow servers to make use of various kinds of accelerators from Intel and third parties.

The vaguest announcement that Intel will make in Beijing is for something called "Larrabee," which is speculated to be an integrated graphics unit, much as rival Advanced Micro Devices is planning to do with graphics chips it got through its acquisition of ATI Technology last year. A graphics chip is a very fast processor, and can be taught to do math as well as to paint pictures. Larrabee has that smell to it, but Maloney would neither confirm nor deny what it is other than it is in silicon, not software. The spec sheet Intel put out says that Larrabee will be "easily programmable using many existing software tools' and is "designed to scale to trillions of floating point operations per second."

Justin Rattner, Intel's chief technology officer, will detail the company's plans to drive down power consumption in mobile computing platforms by a factor of 10 by 2010. He will also show off another iteration of the 80-core TeraFlops experimental RISC chip that it showed off last year at IDF, only this time it will be running at twice the throughput, or a 2 teraflops.

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