Breaking News--Intel Previews Quad-Core Chips, Talks Up Massively Cored RISC

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Intel Previews Quad-Core Chips, Talks Up Massively Cored RISC

Published: September 27, 2006

by Timothy Prickett Morgan

Chip maker Intel is hosting its semi-annual Intel Developer Forum in San Francisco this week, and its future quad-core chips for desktops and servers are the centerpieces of the event. Intel also previewed a future 80-core RISC processor, which appears to be a variant of the i860/i960 family of RISC chips that was used in the Paragon supercomputer in the early 1990s.

Intel has a bunch of quad-core chips in the works. Some of them are the result of putting two Core 2 Duo or Xeon chips side-by-side in a single multichip module and using a single chip socket, while some actually put four chips on a single piece of silicon and plug the resulting chip into a single socket.

The one that is immediately interesting to most IT customers is the Quad-Core Xeon 5300, which is two "Woodcrest" Xeon 5100 processors put into a single package. This chip, which Intel moved forward six months ago, pulling it into 2006 from its original early 2007 launch, is code-named "Clovertown."

Why bother putting two chips in a single package rather than wait for a real quad-core chip? Well, with a 65 nanometer process and plenty of expertise in chip-packaging technology, Intel can get four processor cores into a single socket about nine months ahead of rival Advanced Micro Devices, which is expected to deliver a true quad-core Rev F Opteron family in the middle of next year.

IBM, which pioneered dual-core chip designs with its Power4 chip from five years ago, did not create a quad-core chip, but has instead done the same thing with the Power5+ chips as Intel is doing with the Xeon 5300s. It's cramming two Power5+ chips into a single package it calls a QCM. Such Power5+ QCMs have lower cache memory and lower bandwidth per core, but for many workloads, they can deliver 50 to 60 percent more oomph per socket. This matters to a lot of customers.

The same holds true for Clovertown Quad-Core Xeon 5300s. A dual-core Woodcrest chip has a thermal design point of 80 watts running at 3 GHz. Intel can slow the clocks down a little bit on the Clovertown chips--the chips are expected to run at 1.6 GHz to 2.67 GHz--and generate less heat per core. This lower heat and the physical smallness of a chip made with a 65 nanometer process allows two cores to go into a single package. It also allows Intel to get better yields with a so-called quasi-quad than it would get with a real quad-core chip, which by necessity would be a larger chip and probabilistically inclined to lower yields. (The bigger a chip, the higher the chance it has a defect.)

Intel says that the quasi-quad Clovertown package should deliver about 50 percent more performance than a dual-core Woodcrest chip at the same 80 watt thermal design point, and moving to the faster Clovertowns will push up performance by as much as 70 percent, but will push the heat up to 120 watts. So server makers with a hard 80 watt thermal limit on the chip--perhaps in a blade server--will nonetheless be able to move to a Clovertown chip running at 80 watts that can replace a 65 watt Woodcrest part.

The quasi-quad Clovertown Xeon chip is set to be available in November, and will plug into the same "Bensley" platforms that Woodcrest and "Paxville" Xeon DP processors plug into. The Clovertown E5310 will run at 1.6 GHz and plug into a 1 GHz front side bus; the E5320 will clock at 1.86 GHz, also plugging into the same 1 GHz bus. The E5345 runs at 2.33 GHz and moves up to a 1.33 GHz bus, and the X5355 is the so-called "extreme" part, which will run at 2.67 GHz and use the faster bus, too. Early in 2007, Intel will put out a 50 watt Clovertown part running at 1.6 GHz, dubbed the L5301.

Intel is also expected to put the "Kentsfield" chip, which crams two "Conroe" Core 2 Duo desktop processors into a single package, into the single-socket server and workstation markets as the Xeon 3200. This Xeon 3200 will come into the market during the first quarter of 2007, if all goes according to plan.

This week, Intel is expected to launch the Dual-Core Xeon 3000 series, which is a server variant of the Core 2 Duo chips for desktops, but at single-socket servers and workstations. As we go to press, these have not yet been revealed, except for a mention in a press release.

The company is also putting out the promised Woodcrest low-power part, the Xeon 5148, which consumes 40 watts while running at 2.33 GHz. This chip will give AMD's Opteron 2000 series a run for the money in terms of performance per watt, and will even compete with the elusive Athlon X2 3800+ variant that runs 2 GHz and consumes only 35 watts (including, unlike Intel's chips, a main memory controller).

The most bizarre project that Intel showed at IDF this week was the so-called TeraFlop processor. This is a research project that Intel's chief technology officer, Justin Rattner, showed off to prove that Intel could do massively multicored processors. Specifically, the TeraFlop chip crams 80 simplified RISC processor cores--presumably a variant of the i860 or i960 chips that Intel created for scientific workstations and embedded applications in the late 1980s--onto a single die. Intel said that this chip has a simplified core for processing floating point data, so it is my guess that this TeraFlop chip actually uses the math unit from the i860 or i960. The cores run at 3.1 GHz in the prototype, and are put in an 8x10 array on the chip. A router to link them is embedded in the silicon, too. This router also links the floating point units to memory.

Speaking of which, the TeraFlops processor also has a 20 MB SRAM that is stacked on top of the chip and bonded to it. Because the SRAM memory is bonded directly to the cores, Intel could put thousands of connections between the processors and the memory, rather than the hundreds that link a CPU to an outside memory bus. This chip and memory stack can deliver teraflops of number-crunching performance and multiple terabytes of memory bandwidth. This is a stunning achievement, particularly when you consider that the Paragon supercomputer, which Intel built for the U.S. government in 1995 using 6,768 of Intel's i860 processors, had a peak performance of 338 gigaflops.

Intel is hoping to deliver a product based on this TeraFlops prototype within five years. However, it will very likely be used as a co-processor, with a Linux operating system running on whatever Xeon-style processor Intel offers at the time. Based on past history, Intel might even be inclined to package this TeraFlops processor in a single chip package next to another general-purpose Xeon-style chip. It could also plunk a Xeon core on the TeraFlops die and integrate it right in the silicon, much as IBM has done with a PowerPC 970 core on the Cell chip.