Intel Begins Dual-Core Xeon Server Chip Rollout
by Timothy Prickett Morgan
After taking a pretty heavy beating in the press and a much less intense drubbing in a server marketplace where every other major chip maker has dual-core chips in the market, Intel joins the ranks today as it begins delivering its "Paxville" Xeon DP chip. Getting the Paxville Xeon DP processor to market is a stop-gap measure until the "Dempsey" Xeon DP, a true dual-core chip with lots of new goodies, comes to market early next year.
While Intel's partners have been shipping its "Smithfield" Pentium D processors in single-socket servers for a while, the Xeon DP is the undisputed and, until recently, unrivaled workhorse of the volume server market. Xeon DPs and their equivalents are what matter for the bulk of server buyers. The Paxville DP is used in two-socket servers and is supported by the existing "Lindenhurst" E7520 chipset as the single-core "Irwindale" Xeon DP processors launch early this year. The Dempsey Xeon DP will offer more performance, consume less power, and generate less heat than the Paxville DP, but the latter chip has two virtues: it is available now and Intel can try to charge a premium for it as we enter the fourth-quarter IT buying blitz.
Intel did not originally intend to put a Paxville DP into the field, but with AMD's launch of its dual-core Opteron processors in April and a ramp for shipments for single-, dual-, and quad-socket configurations through the summer, Intel had to do something to answer AMD. So it took two Irwindale Xeon DP cores, each with their own 2 MB L2 cache on chip and with 64-bit memory extensions and HyperThreading, and implemented them in a 90 nanometer process on a single piece of silicon. The Paxville DPs have an 800 MHz front side bus, which is shared across the two cores. And even though Intel is trying to charge a premium for the Paxville DP, it will at least partially blunt the progress Advanced Micro Devices is making in the X64 server space. AMD was first to market with 64-bit memory extensions in 2001 for server chips, and this year it beat Intel handily in the race to get dual-core processors to market.
But the Paxville DP chip has one big advantage: it plugs right into existing Lindenhurst machines, and there are a lot of them out there in the world. Moreover, according to Shannon Poulin, director of product marketing for Intel's Server Platform Group, while most server customers are obviously keen on getting the best technology and some of them might rather prefer to wait for the Dempsey Xeon DPs and their associated "Bensley" server platform--which has integrated virtualization, I/O acceleration, and system management features that are missing in the current Xeon DPs, as well as support for dual 1.066 GHz front side buses (delivering 17 GB/sec of bus bandwidth compared to the 6.4 GB/sec of the single bus used in the Lindenhurst E7520 chipset), and fully buffered DIMM main memory--there are nonetheless a very large number of customers who need to buy hundreds or thousands of servers a quarter each, and they just want something that is better than a single-core Xeon DP box right now. They need some price/performance improvements, and Paxville DP will do the job.
"When we brief customers on the roadmap, they tell us that the Paxille and Dempsey/Bensley platforms are pretty complementary," says Poulin. He says that Intel is currently sampling thousands of Dempsey/Bensley platforms right now to its OEM server customers, and that Intel expects to meet its first quarter launch goals for the new Xeon DP platform.
The Paxville DP chip is only available in one speed, which is 2.8 GHz. It comes with 2 MB of integrated L2 cache per core, and with the doubling of cores, a two-socket server can now deliver eight processor threads (including the HyperThreading virtual threading). The Paxville DP also includes support for 400 MHz DDR2 main memory, Execute Disable (XD) security, and Demand Based Switching (DBS) power management features, just like the Irwindale chips. In 1,000-unit quantities, Intel is charging $1,043 for the Paxville DP. In terms of performance, Poulin said that a dual-core 2.8 GHz Paxville DP would deliver anywhere from 30 to 50 percent more oomph on server workloads compared to a single-core Irwindale Xeon DP running at 3.6 GHz. Back on September 11, Intel dropped the price of the top-end Irwindale Xeon DP by 19 percent to $690, which increased the performance premium it is charging for the Paxville DP. Basically, if you want 30 to 50 percent more performance in a Lindenhurst server, you have to pay 51 percent more for the chip today.
In addition to talking about the Paxville DP chip, Poulin also said that within the next 60 days--"and probably before that"--Intel would be rolling out the Paxville Xeon MP processor, which is used in higher-end machines that have four processor sockets per motherboard. Intel had been expected to deliver the 90 nanometer Paxville Xeon MPs sometime early next year, but in August moved the delivery up because it was getting good yields on the 90 nanometer process. (This was also when the Paxville DP, which was not on the roadmaps, made its sudden appearance.) The Paxville MP, like the current Xeon MPs, support PCI Express I/O as well as the other features supported in the Paxville DP platforms. The current "Potomac" and "Cranford" Xeon MPs were the first 64-bit Xeon MPs, and they have only been shipping for a little while. They have a 667 MHz front side bus and use the E8500 chipset. With the Paxville MPs, Intel is tweaking the chipset to make the E8501, which will support an 800 MHz front side bus for the dual-core Paxville MPs. The Paxville MP/E8501 combo will still be considered a "Truland" platform, for what it's worth, but the chip will have the name of the dual-core Xeon Processor 7000. Customers will also be able to get versions of the Paxville MP processors that support the slower 667 MHz bus speeds of the E8500 chipset, which provides some investment protection.
Intel is being a little cagey about what clock speeds to expect with the Paxville MPs, but 3 GHz looks to be the top end speed, says Poulin. If history is any guide, the top-end part will run at 3 GHz and have both L3 caches at their full strength of 8 MB per core; then, Intel will probably offer versions of the chip running at lower clock speeds and with half the caches activated. (By offering different speeds and feeds, Intel increases yields.) I would guess that Intel will have 2.67 GHz and 2.8 GHz Paxville MPs with 1 MB and 2 MB L2 caches. The large-cache "Tulsa" kickers to the Potomac Xeon MPs are not due until the second half of 2006. The good news is that the Paxville MP platforms will be upgradeable to the Tulsa MP platforms, since they use the same E8501 chipset. The Paxville MP platforms are expected to deliver anywhere from 40 to 60 percent more performance than the single-core 3.66 GHz Cranford/E8500 platforms.
While Poulin talked up the Paxville DP and MP chips, he wants to make it very clear that this is just the beginning of the dual-core ramp up for Intel. He says that the Dempsey/Bensley platforms will offer about twice the performance as the current Irwindale/Lindenhurst platforms, and do so with about 50 percent better performance per watt. (That's only a 33 percent performance improvement over the Paxville DP platforms, though.) Similarly, the Tulsa MPs will offer about twice the performance as the current Potomac and Cranford Xeon MPs (and about 33 percent better performance than the Paxville MPs). It is the move to 65 nanometer technology that will allow Intel to radically improve the performance per watt with the Dempsey chips in the first quarter of 2006 and the Tulsa chips in the second half of 2006.
The question is how these chips will stack up to dual-core Opteron servers in the same class. This is a subject I will return to in a future story. Stay tuned.