Intel Draws More Lines on Xeon, Itanium Roadmaps
by Timothy Prickett Morgan
The beginning of Intel Developer Forum is always about the big ideas that set the themes for the show and generally chart the course for where Intel wants to take the IT industry (or where Intel think the IT industry is going to take it). Day two is about the giving a little more detail--but just enough to whet the appetite. And last week Mike Fister, general manager of Intel's Enterprise Platforms Group, said just enough about its Xeon and Itanium processor plans for the next two years to make its systems partners hungry without telling them everything that is on the menu.
Only a few weeks ago, Fister had laid out how Intel's long-term plan was to keep the Itanium processors delivering twice the performance as Xeons and getting the cost of the server platforms at parity by 2007. There will be a lot of processors, related chipsets, and chip-making processes announced before that can happen.
Taking it from the bottom up, Fister said that the "Nocona" Xeon DP processors that Intel would deliver in the second quarter--and the first processors to support the new 64-bit memory extensions that we the talk of IDF this week--would run at 3.6 GHz and would have 1 MB of L3 cache memory.
Up until now, Intel had not divulged the feeds and speeds of Nocona, other than to say that the chips would support 400 MHz DDR2 ECC main memory and an 800 MHz front side bus. The Nocona will support the "Lindenhurst" chipset for dual-processor servers and the "Tumwater" variant aimed at high-end workstations; motherboards based on these chipsets will be able to support up to 16 GB of main memory in four slots using 4 GB DIMMs that use considerably less power and generate a lot less heat than machines using 1 GB or 2 GB DDR DIMMs.
The future "Jayhawk" kickers to Nocona will also work in the Lindenhurst and Tumwater chipsets, and are probably Nocona's with larger cache and more features activated that are latent in their cores (like HyperThreading was latent in the prior "Northwood" Pentium 4s and 64-bit was latent in the new "Prescott" Pentium 4s). Further out in 2005, Intel will deliver new chipsets that support the Jayhawks as well as an as-yet unnamed successor to them in the Xeon DP line.
Intel didn't really say much more about the Xeon MP machines this week at IDF. Intel is expected to imminently announce a 3 GHz version of the "Gallatin" Xeon MP with 4 MB of on-chip L3 cache memory, which will plug into existing Gallatin machines. It won't be until early in 2005 that Intel will start shipping the "Potomac" kickers to Gallatin, which will use a beefed up variant of the Lindenhurst chipset called "Twin Castle" that supports DDR2 main memory, 64-bit addressing, and an 800 MHz front side bus.
In the second half of 2005, Intel will roll out a dual-core implementation of Potomac called "Tulsa." It is not yet clear if the Tulsa processor will support HyperThreading as well as chip multithreading. In an interview, Fister hedged and said that Intel was keeping its options open and that in some cases, it might make sense to have both dual-cores and HyperThreading in the same chip.
Fister said that all of the Xeons going forward would support three different modes: 32-bit applications on 32-bit operating systems, a so-called legacy mode; 32-bit applications running in "compatibility mode" on a 64-bit capable operating system; and a full-blown 64-bit mode for applications running on a 64-bit operating system. While he did not get into the nitty gritty of how the 64-bit extensions are implemented, he did say that the new Xeons would have 64-bit pointers and registers, would include 64-bit double precision integer processing, would have eight new SSE registers and eight new general purpose registers, and would support a flat virtual address space.
On the Itanium MP front, Fister said that the updated "Madison" Itanium 2 processor that is expected in the second half of this year would include 9 MB of L3 cache and would run at 1.7 GHz. It will probably provide about 15 percent more performance on workloads that don't care all that much about L3 cache than the current 1.5 GHz Madison chip, but could do a bit better than that on cache sensitive applications.
Fister didn't say much new about the dual-core "Montecito" Itanium due in 2005, which will be built using Intel's 90 nanometer chip making technology and have a gigantic 24 MB L3 cache. Beyond that, the "Tukwila" Itanium chip, which is being designed in conjunction with the engineers Intel picked up from the defunct Alpha processor team from Compaq, will come out in 2006, probably with four cores on a single chip.
The news at this IDF was centered more on the Itanium DP front. The current "Deerfield" Low Voltage Itanium 2 DP processors, which ship in two-way servers aimed primarily at HPC clusters, current run at 1 GHz or 1.4 GHz and have 1.5 MB of L3 cache. Later this year, Intel will launch a new Itanium DP chip dubbed "Fanwood" that will come in the regular DP and the low-voltage DP flavors. The Fanwood DP will run at 1.6 GHz and have 3 MB of L3 cache, while the LV Fanwood DP will slow down slightly to 1.2 GHz and have 3 MB of L3 cache.
In 2005, when the dual-core Montecito Itanium MPs ship, Intel will ship DP and low voltage DP variants of this chip called "Millington," and the Tukwila four-core chip will also have these two DP variants as well, known as "Dimona." Intel has not given out any of the feeds and speeds on these future Itanium DP processors, but wanted mainly to make it clear that it will continue to deliver three different styles of Itanium chips for the foreseeable future.
The Montecito chips will use a new chipset called "Bayshore," which will support DDR2 main memory, PCI Express peripheral interconnects and "faster" front side buses. The Montecito chip will also incorporate a new feature called Pellston Technology (PT) that will improve the reliability of data storage in Montecito's cache memories, and another feature called Foxton Technology (FT), that will allow a Montecito chip that is running cooler than its design specs to automatically go into a burst mode to finish processing work quicker so long as the chip doesn't exceed Intel's and user's thresholds for heat output on the chip. Montecito will also have more sophisticated power management features--essentially Intel is going to play with the voltage to keep it cool when workloads are not demanding--thus lowering the electricity usage and heat profile of the Itanium, which has been one of the limiting factors in its adoption in servers.
In addition to these technologies, Intel is working on a variant of the Vanderpool Technology (VT) feature that it demonstrated this week on desktop systems, which enables partitioning of a single Xeon processor into multiple virtual machines. On the server front, a variant of Vanderpool code-named "Silvervale" will be embedded in the Xeon and Itanium server processors that Fister says will borrow ideas from Vanderpool but will in reality add hardware support for virtualization technologies already created by the likes of VMware, IBM, Hewlett-Packard, Microsoft and others for their server platforms. At this point, it looks like Silvervale technology, or ST, is not fully cooked and will merely facilitate physical and logical partitions.
Exactly how this will be accomplished, Fister would not say in the interview, except to say that it will involve a certain amount of standardization among the various server vendors and their very different ways of doing virtualization and that Intel was working with server makers on how best to do this. Silvervale will be available on both Xeon and Itanium processors. Fister did not say when it might arrive on the scene.