IBM Demos 1.5 GHz Four-Way Squadron

by Timothy Prickett Morgan

I took a good, hard look at the first Power5-based "Squadron" server that IBM has publicly demonstrated. The machine, which IBM showed off at its Power Everywhere event in New York last week, was a four-way box that was missing its front label panel. While IBM would not say much about the machine, you can learn a lot if you just look carefully.

The machine that I saw at the show was a four-way box running AIX 5L 5.3, OS/400 V5R3, and a 64-bit Power implementation of Linux, each in its own partition. The machine's hypervisor, which controls the logical partitions, had allocated three partitions across 1.5 processors and still had 2.5 processors not activated, ready to be dynamically added to support the workloads that were running on the box. (There was a Java runtime error, which the tech skipped over very quickly, but the partitions did increase in size, and you could see the Linux workload sigh in relief on a graph as it got more CPU.) This demonstration, I learned, as Al Zollar, general manager of IBM's iSeries division, walked up behind me and started asking questions, was the so-called "board of directors" demo machine that the top brass at IBM had seen recently, running OS/400 and Linux. AIX 5L 5.3 was only just added to the mix.

The Squadron box looked like it was a 4U chassis. It had two processor cards in it, each with a single, dual-core Power5 processor on it with an immense heat sink. It may have had room to add two more processor cards, but the open slots (which had dummy plastic placeholders in them) might have been for other electronic devices. Last year, I had heard that IBM would be able to deliver a two-way 4U form factor that could be used as a rack-mounted server or could be flipped on its side to be used as a tower machine. What those sources must have meant was a two-processor or a four-core server in a 4U box. (This is what happens when you put multiple cores on a single chip. People get confused with their language. I just count the cores, since this is what matters to the software.) When I poked my head in the rack, while the IBMers were looking the other way, I saw that the Power5 processors were clearly labeled as running at 1.5 GHz. This is the low end of the expected clock speed of the chips, which should scale initially to 1.8 GHz or 2 GHz before a crank on the chip making processes, in 2005 or so, allows IBM to reach into the 3 GHz range with the Power5+ chips.

IBM did not demonstrate the expected 8U form factor Squadron machine, but it seems likely that this machine will merely be two four-way, two eight-way, or four four-way Squadron servers, like the one that IBM demoed, but linked through a high-speed, NUMA-like SMP interconnect. This is the same kind of interconnection that IBM uses on the 16-way xSeries 440 (32-bit Xeon MP) and xSeries 445 (64-bit Itanium 2) "Summit" servers. If it works like the Summit boxes, each 8U chassis will have from two to eight physical processors (that's four to 16 cores). I think IBM will link together four four-core Squadrons to make the 16-way box and will use electronics that are very similar to the Summit chipset, which is a variant of the NUMA-Q interconnect that IBM got years ago when it acquired server maker Sequent.

IBM didn't say anything about the bigger Squadron boxes, but the picture of the chip clearly shows four dual-core Power5 processors, which will have simultaneous multithreading that makes it look like there are 16 cores on the die to the operating system. There are also four 36 MB L3 caches integrated onto the multi-chip module, the first time IBM is integrating L3 cache on the chip. Each Power5 core has 64 KB of L1 cache, and the two cores on a chip share a 1.9 MB L2 cache. The top-end 64-way Squadron box will house eight of these Power5 MCMs, which almost certainly will debut at 1.8 GHz or higher. IBM can always crank up the speed on the MCM versions of its Power chips easier than it can on the entry single-chip versions.