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As we anticipated early last month, Intel announced its "McKinley" Itanium 2 processors this week. While Intel has announced the processors and a few vendors have announced that they are taking orders for workstations and servers that use the McKinley processors, it doesn't look like the McKinley chips will ship in appreciable volumes until August. The McKinley chips are a big improvement over the first-generation "Merced" Itanium chips, but they are coming to market almost a year late.

Information leaking out from Intel as well as from other sources had indicated that the McKinley chip would be available at a 1 GHz clock speed with 3 MB of L3 cache memory. The McKinleys actually come in three different configurations. Intel is shipping a 900 MHz version of the chip with 1.5 MB of L3 cache memory, a 1 GHz chip with 1.5 MB of L3 cache, and a 1 GHz chip with 3 MB of L3 cache. The 900 MHz version of the chip is relatively inexpensive, at $1,338 for 1,000-unit quantities, and probably provides somewhere between 1.25 and 1.3 times the performance of the 800 MHz Merced processor with 4 MB of off-chip L3 cache, which cost $4,227. The 900 MHz McKinley costs a little bit more than the 733 MHz Merced with 2 MB of off-chip L3 cache, which cost $1,177. The 1 GHz McKinley with 1.5 MB of L3 cache costs $2,247, which is a slight premium compared to the 800 MHz Merced equipped with 2 MB of L2 cache. Intel is charging virtually the same amount for its top-end McKinley, at $4,226, as it charged for the top-end Merced chip, even though the fastest McKinley offers from 1.5 to 2.0 times the performance of the top-end Merced based on preliminary benchmark data available from Intel.

If you were surprised by the announcement of smaller cache McKinleys as well as ones with a slower 900 MHz clock speed, you are not alone. Intel never gave anyone the impression that it was launching this slower chip with smaller L3 cache, but the company does like to offer a range of different price and performance points with its chips and this is absolutely consistent with past history. It is also likely that yields on the McKinleys with lower clock speeds and smaller caches are higher--the faster a chip runs and the larger it is, the more likely it is that impurities and errors in its nanoscale wiring will cause it to not work properly--and that Intel and its partners will try to encourage companies to buy the slower McKinleys except for the most demanding workloads that require that extra clock speed and bigger caches.

The top-end 1 GHz clock speed of the McKinley chip is the original target top clock speed of the original Merced chips. Both the Merced and McKinley chips are made using a 0.18 micron process. The Merced chips had 10 pipeline stages and nine instruction issue ports that in turn fed into 328 registers. These registers fed into four integer units, three branch units, two floating point units, two SIMD units, and two load/store units, which ran at 800 MHz and 733 MHz. With McKinley, Intel has tripled the system bus bandwidth, moved a smaller (but still quite large) L3 cache onto the chip, removed a few pipeline stages, added issue ports, and tweaked the various computing units inside the chip so a McKinley comes closer to actually processing the six theoretical instructions per clock that the Itanium was designed to deliver. McKinley chips have 1.5 MB or 3 MB of on-chip L3 cache that is linked to a 128-bit, 400 MHz system bus with 6.4 GB/sec of aggregate bandwidth. The McKinley has eight pipeline stages feeding into eleven issue ports, which in turn feed into the same 328 registers. These pass off instructions and data to six integer units, three branch units, two floating point units, one SIMD unit, two load units, and two store units. The changes in the guts of the chip and the increase in clock speed are what make McKinley a better chip than Merced.

Next week, we will review the McKinley server plans of the major server vendors, now that Intel has removed the NDA muzzle that has prevented them from talking specifically about their plans.

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