Mid
Windows & Linux Edition
Volume 1, Number 30 -- September 11, 2002

Intel Talks Up Technologies at IDF, Previews Madison Itaniums


by Timothy Prickett Morgan

Intel is hosting its Fall 2002 Intel Developer Forum in San Jose this week, and the company's president and chief operating officer, Paul Otellini talked up a bunch of existing and forthcoming technologies for its processors. The company also debuted its first machine based on the "Madison" kicker to the Itanium family of 64-bit processors in an ES7000 server from Unisys. Madison and a related chip for dual-processor servers code-named "Deerfield" are expected to debut sometime next year.


Much of what Otellini talked about in his IDF keynote speech had to do with technologies that will end up in the processors that Intel makes for desktops, but some of the technologies could end up in server processors, too. In general, he said that 90-nanometer chip making process technologies, which Intel will begin rolling out next year in the 64-bit Madison and Deerfield chips, among other products, would allow Intel to begin converging communications technologies on its processors, pushing on-chip integration out beyond processors and memories to the networking devices that connect desktops and servers to each other. He said that Intel has already been planning for chips that incorporate one billion transistors on a single piece of silicon. That is five times the transistors of the largest processors available today, the dual-core Power4 RISC chip from IBM at 200 million transistors and the Itanium 2 from Intel at 220 million transistors. The first step in this integration will be the "Banias" mobile Pentium III-M mobile processor, which will have wireless communications controllers adhering to the 802.11a and 802.11b standards integrated into their processor modules. He also showed off a 4.1 GHz prototype Pentium 4 processor, which he then overclocked to 4.7 GHz before it caused the test machine to crash.

Otellini demonstrated a 3 GHz Pentium 4 processor using the HyperThreading simultaneous threading technology that debuted in the "Prestonia" 32-bit Pentium 4 Xeon DP processors for workstations and servers earlier this year. This 3 GHz Pentium 4 desktop processor will debut later in the third quarter. Intel has said that hyperthreading, which keeps the chip pipelines full by making compilers behave as if there are two virtual processors at their disposal for multithreaded applications instead of one real one, can boost performance on the desktop by about 25 percent and on servers by as much as 30 percent. The interesting statistic from Otellini regarding hyperthreading is that Intel expects more than 25 percent of the performance desktop machines it ships in 2003 to be based on chips that support hyperthreading, with 60 percent of workstation processors and 80 percent of server processors having the technology. Hyperthreading will quickly become pervasive, and it will be up to application providers to start taking advantage of this feature.

One of the other interesting technologies that Otellini debuted was code-named "LaGrande," and it is on-chip security for future Intel processors that will incorporate a new microarchitecture (think Pentium 5) with the goal of delivering protected execution, protected memory, and protected storage modes that prevent system hacking and tampering through processor and chip extensions. In essence, sensitive data that is vital for the operating system, applications, and e-business is stored in an encrypted, secure areas in memory and disk that cannot be tampered with from outside the machine.

Finally, Otellini demonstrated a hot-swap upgrade of a four-way cell board in a Unisys ES7000 using the new 1 GHz "McKinley" Itanium 2 processors to a future four-way cell board based on the Madison processors. While Otellini did not say what the eventual clock speed of the Madison processor would be, we do know that it will be based on the 90-nanometer manufacturing processes that Intel will start using next year and that Madison will have 6 MB of on-chip L3 cache memory, twice that of the McKinley chips. Otellini said that the Madison chip, which could be branded as the Itanium 3, will include nearly 500 million transistors--more than twice that in the McKinleys--and that it will have about 30 percent better performance. This suggests a clock speed of between 1.2 GHz and 1.3 GHz for the initial Madison chips. The Deerfield variants of these so-called Itanium 3 processors could run at higher clock speeds and will likely have far less cache memory integrated on their chips. The Madison chips can be plugged directly into machines that use the Itanium 2 chips, and have been prototyping with Windows, Linux, HP-UX and possibly other operating systems since sometime in June.


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BACK ISSUES

TABLE OF CONTENTS
NEC Shows 32-Way Windows Server with Unix-Class Oomph

Intel Talks Up Technologies at IDF, Previews Madison Itaniums

Microsoft to Support Multipath I/O in Wintel Servers

inFORM Decisions Launches Document Management for Windows



Editor
Timothy Prickett Morgan

Managing Editor
Mari Barrett

Contributing Editors
Dan Burger
Joe Hertvik
Shannon O'Donnell
Victor Rozek
Hesh Wiener
Alex Woodie

Publisher and
Advertising Director

Jenny Thomas

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Last Updated: 9/11/02
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