Guild Companies

It was the fall Intel Developer Forum last week, and the bigwigs at Intel assembled the multitudes in San Jose to give them a sneak peak at future processor and related technologies and a view of how they see the world of computing. While the theme of communications-computing convergence that Intel has been talking about for year is interesting, what most people in the enterprise want to know is what Intel is going to do with its processors.

To that end, Paul Otellini, who is president of the company, raised the curtain a bit on future 32-bit Pentium 4 Xeon and 64-bit Itanium processors. He also gave some background on the current and expected adoption rates of specific technologies that Intel thinks are key.

Before discussing the processors themselves, Otellini spoke about the company's hyper-threading technology, which is an implementation of what most of the computer industry refers to as "simultaneous multithreading." Hyper-threading technology takes two instruction pipelines inside of a processor core and rejiggers the streams of instructions inside of them in such a way that the processor can present a view of two virtual cores to the operating system running on that processor, instead of one. Hyper-threading technology can boost performance by a considerable amount: maybe 25 to 30 percent on certain workloads. Hyper-threading technology only costs a little, in terms of transistor count, and it boosts performance without the need to boost clock speed. This cuts down on the electricity that a chip needs to operate and the heat that it dissipates. It is no surprise, then, that Intel has been weaving hyper-threading technology into its processors as fast as it can.

Otellini said that Intel has implemented hyper-threading technology in the current Xeon DP and MP processors for two- and four-way or larger servers. By the end of the year, he estimates, the use of chips with hyper-threading technology will exceed 50 percent of the "performance desktops" that Intel's partners sell using its chips, and he predicted further that hyper-threading technology would be "pervasive" by the end of next year, by which he means, presumably, that all new laptops, desktops, and servers selling would have hyper-threading technology inside of their Intel chips. While the Itanium processors do not yet have hyper-threading technology embedded in them, the obvious benefit to performance that hyper-threading technology would bring, particularly to multithreaded applications like Web servers and databases, means that Intel is clearly working on this.

While hyper-threading technology can help boost performance by presenting two virtual cores to an operating system and its application for every one real core, performance can also be boosted by putting multiple cores on a single chip. IBM has already done this with its Power4 processor, and Hewlett-Packard and Sun Microsystems are working on dual-core processors with their respective PA-8800 and UltraSparc-IV processors, which are due near the end of this year or early next year. Earlier this year, Intel committed to bringing out the dual-core implementation of the Itanium processor, code-named "Montecito," sometime in 2005.

At the IDF conference last week, Otellini said that the "Tanglewood" implementation of the Itanium processor (which will come to market sometime after Montecito) will have "multiple" cores, which probably means four, but it could mean six or even eight, depending on how ambitious Intel wants to be and where various chip-making processes are in terms of yields. The Tanglewood chip is being designed by Intel Itanium engineers, as well as a team of chip designers from the former Compaq (well, actually, the former Digital Equipment) who were working on the EV8 and EV9 versions of the Alpha processor before Compaq shuttered that business and sold off the intellectual property for Alpha, along with the people who worked on it, to Intel. All that Otellini would say about Tanglewood, besides that it exists and is being designed by this hybrid Itanium-Alpha team, is that it would deliver seven times the performance of the current 1.5 GHz "Madison" implementation of Itanium.

What might such a chip look like? It is hard to say, but let's take a stab at it. Say you added hyper-threading technology to the Madison core and made four cores share a single L3 cache of 6 MB capacity. If you could do that with Madison today running at 1.5 GHz, each Madison core would perform like a 2 GHz core on multithreaded applications just because of the hyper-threading technology. Making the four cores share that L3 cache on-chip would present some overhead, just like symmetric multiprocessing does on servers, but maybe a four-core Madison might deliver 65 to 75 percent of the aggregate performance of those four processors where the rubber hits the road. When you combine the effects of hyper-threading technology and multiple cores, a 1.5 GHz version of the four-core Madison would deliver about the same performance as a single Madison core running at 5.46 GHz. If you could jack up the clock speed on this theoretical device to 3 GHz, it would have about 7.3 times the performance as a 1.5 GHz single-core Madison.

On the 32-bit front, Otellini also talked a little bit about the future Xeon processors dubbed "Potomac" and "Tulsa."

Intel already talked about some of the chipsets for these machines back in June. In 2004, Intel is planning to introduce the "Lindenhurst" chipset, for future Xeon DP processors for two-way workstations and servers, and the "Twin Castle" chipset, for future Xeon MP processors for four-way servers. These two chipsets will incorporate support for PCI Express point-to-point I/O interconnections and will also support DDR2 memory subsystems. The Lindenhurst chipset is expected to be matched with the future "Jayhawk" Xeon DP processor in the second half of 2004, while the Twin Castle chipset will work with the future Gallatin chips with 4 MB integrated L3 cache, due in early 2004, and the "Potomac" Xeon MP chips, due in the second half of 2004.

Otellini didn't talk at all about the Jayhawk Xeon DP processor, and he did not get into specifics about Potomac other than mentioning it as the future Xeon MP processor. He didn't say much about the Tulsa Xeon processor, either, except to say that it would be a dual-core implementation of the Pentium 4 Xeon processor and that it would include hyper-threading technology, as all the Xeons now do. The word on the street is that it will take Intel two to three years to actually get Tulsa out the door. That puts it anywhere from concurrent with Intel's first 64-bit dual-core chip, the Montecito Itanium, to a year after it. He said even less about when multiple-core Pentiums and Itaniums might appear for desktop and laptop computers, but he hinted that they would come eventually.

Mike Fister, general manager of Intel's Enterprise Platforms Group, fleshed out the roadmap for the Xeon line a little bit more than Otellini did a few days earlier. Fister's roadmap shows that a "Gallatin" Pentium 4 Xeon MP processor running at 3 GHz and with 4 MB of L3 cache was due in late 2003 or early 2004. The Potomac Xeon MP would have a larger cache and higher clock frequencies enabled by the move to 90 nanometer chip processes. In the Xeon DP line, the current "Prestonia" chips have 1 MB of L3 cache and run at a top speed of 3.06 GHz. The future Nocona Xeon DP chip, due in early 2004, will run at 3.2 GHz and will sport an 800 MHz frontside bus; it will be implemented in a 90 nanometer process as well. The Jayhawk Xeon DP, due in late 2004 or early 2005, will be the same chip but with a higher clock rate. Just how high, Intel is not saying.

One of the cooler new things that Otellini talked about was another virtualization technique called Vanderpool. With Vanderpool technology, Intel is going to weave hardware-based processor partitioning into the future Intel product line. Otellini says that this will happen within the next five years, which is not a very aggressive rollout considering that RISC/Unix servers and proprietary machines have had this virtualization for years.