Power5 Means Powerful iSeries Iron Is Possible

by Timothy Prickett Morgan

If you're worried about the amount of headroom IBM can deliver in its top-end iSeries servers, or that IBM's Power line of chips cannot keep pace with commodity Intel processors or competing RISC chips from Sun Microsystems, Fujitsu, or Hewlett-Packard, fear not. IBM's got big plans, suitable for large and small servers alike, for its future Power5 processors. These chips will eventually play into the iSeries product line, and will bring a lot of power to bear on OS/400, Linux, and AIX workloads.

Back in May, we told you as much as we knew about the future Power5 processors and their associated "Armada" kickers to the Power4-based "Regatta" line of machines that are currently being sold under the iSeries and pSeries monikers. What we knew about the Power5 chips was a little bit vague, but sources familiar with IBM's plans have firmed up what IBM will deliver starting in early 2004.

Back in May, all we knew for sure was that the Power5 processors, due sometime in late 2004 or early 2005, in the Armada servers, would eventually have a cycle time that is lower than 0.7 nanoseconds. This was a very general statement, not a specific one, and from that we reckoned that IBM would try to crest the 2 GHz mark with the Power5 processors. We guessed that the initial Power5 processors might run in the 1.9 GHz to 2.1 GHz range. According to our sources, the Power5 chips--which will be implemented in the same 0.13 micron process used to create the 1.2 GHz and 1.45 GHz Power4+ processors, used in the eight-way pSeries 650 machines IBM announced in November 2002--initially will run at around 1.5 GHz, and IBM hopes to be able to scale them to above 2 GHz clock speeds without resorting to 0.09 micron chip-making processes, which apparently will be used to deliver the Power5+ processors sometime in 2005.

The Power5 and Power+ chips will be, like the Power4 and Power4+ chips they replace, dual-core processors with a shared L2 cache memory and external L3 caches integrated on multichip modules. The Power4 MCMs had 1.44 MB of L2 cache, and the Power4+ chips have 1.5 MB of L2 cache on each dual-core chip. With the Power5 chips, IBM will jack up the size of the L2 cache to around 1.9 MB to 2 MB. The main memory controller and L3 cache controllers will also be put inside the chip, which will reduce latencies and speed up throughput.

We also knew back in May that the Power5 chips would support simultaneous multithreading, a technology that allows a single multipipelined processor to present two virtual images of itself to an operating system. Simultaneous multithreading has been implemented in the two-way "Prestonia" and four-way "Gallatin" Pentium 4 Xeon processors, from Intel, by the name HyperThreading. The few remaining chip vendors like Sun and Fujitsu will be adding simultaneous multithreading support to their processors, too, since it can boost performance by anywhere from 25 to 30 percent on certain workloads without substantial changes to the chip. (The operating system and applications have to be tweaked and recompiled to support simultaneous multithreading, however.) When IBM said it was going to deliver 64-way Armada servers, it wasn't clear that the machines would be real 64-way machines, or if IBM was counting simultaneous multithreading running on a 32-way machine (like the current iSeries Model 890 and pSeries 690 Regatta-H servers) as a 64-way machine, which it sort of is. Lo and behold, our sources at IBM say the top-end Armada machine will be a true 64-way machine, and that the SMT support will be grafted on top of this, yielding a virtual 128 processors for OS/400, Linux, and AIX to play with. The Armada machines will also support at least 512 GB of main memory--something IBM apparently intends to support on the pSeries 690 sometime this year--and, given the advances in memory technology, Big Blue might even bump this up to 1 TB of main memory for some Armada machines. (This large memory might be available only on pSeries for a while.)

Industry observers had not been expecting Power5 machines until October 2004, but it seems IBM has lit a fire under the Armada technology to keep pace with the 64-way and 128-way Itanium-based "Pinnacles" and 128-way PA-8800-based Superdome servers from HP, which will be rolling out in 2003 and 2004. The core 64-way Power5 Armada machine could easily hit 1 million transactions per minute (TPM) on the TPC-C online transaction processing benchmark test, which is the same performance level HP is aiming for with the future Pinnacles and Superdome machines. If IBM adds database acceleration electronics to the Power5 multichip modules, gets good efficiencies on SMP and L2/L3 cache hit rates, and does a lot of tuning, it could hit a much higher TPM rate. We have been hearing talk about a whopping 2 million TPM rate on the initial Armada machines, but have been unable to nail that number down. At 1 million TPM, that is just under three times as powerful as the current top-end iSeries Model 890 (roughly 93,000 CPWs, in OS/400-speak) using 1.3 GHz Power4 processors. A 2 million TPM machine--which would presumably be possible because the Power5 MCM would have a lot of other adjunct chips to boost DB2 table lookups, for instance--would yield about 185,000 CPWs of raw power, or about five times that of the current iSeries Model 890.

What is still not known is when IBM will roll out the Power4+ chips in the iSeries Regatta machines. These chips have not been rolled into the 32-way pSeries 690 frames yet, and the odds favor them appearing in the pSeries line a good six to nine months ahead of when they appear in the iSeries line. An iSeries 890 machine with a 1.45 GHz Power4+ processor should have a rating of about 42,000 CPWs, compared with the 37,400 CPW rating for the iSeries Model 890 using a 1.3 GHz Power4 processor. If IBM uses a 1.7 GHz Power4+ processor, which we hear it will try to deliver eventually, that future 32-way iSeries 890 machine could hit around 48,000 CPWs. Because this is not a big boost in performance, IBM might forgo the Power4+ generation for the top-end machines and just jump in with the Power5 boxes in 2004. A lot depends on market demand. And in a pinch, OS/400 customers who have run out of gas on an iSeries Model 890 using the current Power4 chips can always work with IBM to get the faster chips on a special-bid basis.

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