More on IBM's eServer i5 Plans for 2005 and 2006

by Timothy Prickett Morgan

Back in December, I gave you a preview of IBM's plans for the eServer i5 line in 2005 and beyond. While I was at the COMMON midrange user group meeting in Chicago two weeks ago, I sat down with Jim Herring, director of iSeries product management and business operations, and chatted about what was coming down the pike and learned a little bit more than I knew a few months ago.

I know that many people in the iSeries market are trying to figure out how to use all of the processing capacity in their Power5-based i5 machines, but the pace of competition in the Unix market is still intense and that means IBM has to keep cranking up the performance on the Power processors to compete. To that end, Herring said IBM has long since finished up the design of the Power5+ chips and is testing the chips in the i5 and p5 servers right now. We can expect announcements of processor upgrades for the i5 and p5 lines some time in the second half of 2005.

While IBM is kicking out a faster Power5+ processor, Herring said there would not be any new additions to the iSeries family this year. With the Power4-based iSeries 8XX servers announced in January 2003, IBM had a couple of gaps at the low-end and in the midrange of the iSeries line, but with the current i5 line, Herring said there are no gaps and therefore IBM does not need to add machines. The rack-mounted, Power5-based two-way p5 510 and eight-way p5 575 servers have not been branded as i5s, and this is not going to change in 2005. IBM does not believe that i5 customers want a dense, rack-optimized server solution for entry workloads. But rest assured, if you want to start a supercomputer based on OS/400 or if you want to launch a service provider business based on OS/400 servers, you can undoubtedly special bid these dense 1U and 2U machines from IBM and put OS/400 on them. They can technically support OS/400.

The Power5+ chip will be a shrink of the current Power5 chip, which is based on a 130 nanometer, copper/SOI process used first in the 1.7 GHz Power4+ chip that came out in July 2003 and was subsequently used to create the 1.9 GHz Power4+ in February 2004. With the Power5+ chips, IBM is moving to a 90 nanometer copper/SOI process. There are two upsides for Power5+ chips for IBM: first, because the chips are smaller, they can run a lot cooler and deliver the same performance at the same clock speed. Second, because they are smaller, the odds of a random imperfection on the chip are a lot smaller, which means the yield on the chips will be a lot higher and the cost of manufacturing the chips will be a lot lower. IBM can pocket the savings as profits or pass them on as price cuts as market conditions dictate. I think it is safe to assume IBM might cut prices a bit and pocket the rest as profits. Herring did not say how far IBM will push up the clock speed on the Power5+ chips. The Power5s run at 1.5 GHz and 1.65 GHz in the i5 line, and they run at these speeds as well as at a faster 1.9 GHz in the p5 line. IBM will probably offer a wider variety of clock speeds for the Power5+ generation, allowing customers to push into the 2.5 GHz to 3 GHz range for machines with about the same CPU thermals, and down into the 1.5 GHz range for customers who want the same performance as the Power5s with about half the heat. That's what I would do, anyway.

Herring also said that IBM is finishing up on the design for the next-generation Power6 processors and is working toward first silicon of that processor. As I said in December, the initial Power6 chips will use the 90 nanometer process used for the Power5+, and then the Power6+ chips will use a future 65 nanometer processes. IBM has said that the leap from Power5 to Power6 will involve a big jump in gigahertz--more than the jump from Power4 to Power5. The fastest initial Power4 clocked at 1.3 GHz, and the fastest Power5 clocks at 1.9 GHz, which is a bump of 46 percent. It seems likely that Power6 chips will probably start out at 3 GHz and push up to 4 GHz. If it can keep the Power6 in the same thermal envelope of the Power5s, there is no reason not to do this. As an alternative, IBM could keep the clock speed relatively low on Power6 and crank up the number of cores on the chip from two to four. However, this will decrease yields and increase the cost of the processor, and that appears to be something IBM does not want to do.

Moreover, IBM has warned me that rather than try to move to four cores on a single die, the Power6 design might shoot to be a low-cost, dual-core chip. With the performance advantages Power already has over other RISC and Itanium chips, IBM does not need to crank up the core count to compete. That's why I think IBM will be moving more components onto the Power6 die (and quite possibly electronics to support zSeries workloads). Look at the trend line: The Power4 chip put two cores with their own L1 caches, the L1 cache controllers, a shared L2 cache, and a single L2 cache controller onto the chip and put the L3 cache off the die. With Power5, IBM added simultaneous multithreading (SMT), boosted the size of the L2 cache, moved the L3 cache controller into the chip, and moved the L3 cache into the chip package. As I have speculated before, I think Power6 will include an on-die L3 cache and an integrated L4 controller, at least for the high-end server variants of the chip, and L4 cache memory possibly in the chip packaging. (If IBM stays with this hierarchical cache structure at all. It is equally possible that IBM does something completely funky with Power6 to boost memory bandwidth beyond what is possible with a staged cache architecture.) The Power6 chips will also reportedly add a lot more functions for self-management from the microcode underpinning OS/400 and AIX into the chip itself. It would not be surprising for the large pieces of the virtualization embodied in the Virtualization Engine to somehow be implemented in chip transistors and firmware loaded into the processor.

More on IBM's i5 Storage Plans

As I explained back in December, IBM is cooking up some storage announcements for the i5 line for the second half of 2005. IBM has been pretty vague about what these might be--until now, that is. According to Herring, starting with the Power5+ generation, IBM is going to do away with the idea of requiring IOPs for storage. That doesn't necessarily mean you won't be allowed to keep your IOPs and storage towers, but the architecture of the i5 is moving closer to that of the p5, which has the central CPUs handle I/O as well as data processing (as all Unix servers do). The AS/400 architecture was always unique in that it supported what is really asymmetric multiprocessing, with relatively modestly powered central processors hooked to legions of intelligent I/O processors that were equipped with microcode that allowed them to run what would otherwise be thought of as jobs suited for a central operating system. Going forward, IBM is doing away with this architecture, said Herring, as much to get the i5 and p5 lines in synch as to improve the availability of the i5 servers. "IOPs don't break very often," he said, "but if you don't have them in the system in the first place, they can never break."

Further on the storage front, Herring said that iSeries customers are interesting in getting tighter integration between external storage area networks (SANs) and their iSeries and i5 machines. The difficulty of moving to a SAN architecture for storage with the iSeries has to do with the much-praised single-level storage in the platform. First, OS/400 needs to boot locally as it is currently written, Moreover, OS/400 needs to have both main memory and disk to create its single-level memory, and OS/400 doesn't share well. But the techies in Rochester are working on a way to boot OS/400 across a SAN fabric. Moreover, IBM is also working on a way to allow HA software to failover one server attached to a SAN to another server attached to the same SAN. To use Herring's words, this is like using a SAN as a logical independent auxiliary storage pool (iASP).

Plans for i5/OS V5R4

As far as OS/400 software goes, we can expect a new release of the iSeries operating system, presumably called i5/OS V5R4, some time in 2006. Herring held his cards pretty close to his chest on exactly what would be in V5R4, but he said that it would include user interface, clustering, and database enhancements. "It will have oodles and oodles of requirements fulfilled," he said with a smile, comparing it to the jump from OS/400 V4R5 to OS/400 V5R1 a few years ago.

Further down the line, he said the next big operating system release--presumably called i6/OS V6R1--would not be tied to any particular hardware release, which suggests that whatever Power6 is, it is not radically different from Power5. Interestingly, with this future OS/400 version or release (depending on what IBM names it when it comes out in 2007 or so), one of the big changes will come with the operating system interface.

IBM created a user interface language called Abstract User Interface Markup Language, which was developed by software engineers at IBM's Rochester and Raleigh, North Carolina, labs. IBM has been using AUIML, which is a derivative of XML, for the past couple of years to create user interfaces for its products. (You can take a look at AUIML at IBM's alphaWorks Website.) AUIML snaps into the open source Eclipse framework that IBM and many other application development tool vendors are supporting.

Herring said OS/400 admins have to wrestle with five different interfaces--including several green-screen interfaces, iSeries Navigator and OpsNav, and now the Hardware Management Console--to manage an iSeries box. "This seems a bit much for your average SMB customer." To that end, IBM will be redesigning the task-oriented OS/400 screens using AUIML and give it all a consistent look and feel. He also hinted that the Rochester team liked WebSphere Portal Express and that OS/400 functions would also start exploiting this technology to make OS/400 a little more user friendly.