IBM Debuts Baby pSeries Regattas, Could Move Up iSeries Regattas

by Timothy Prickett Morgan

In addition to the new baby Regatta pSeries servers, which are expected to start shipping on April 26, IBM is expected to crank up the clocks on the S-Star processors in certain models in its pSeries 620 and pSeries 660 families of machines. These machines, which currently use 450 MHz Pulsar, 500 MHz I-Star, and 600 MHz and 668 MHz S-Star processors with either 2 MB or 4 MB of L2 cache memory, will now be equipped with the 750 MHz S-Star chips, which have 8 MB of L2 cache. The 750 MHz S-Stars, the fastest 64-bit uniprocessor chips that IBM makes, made their debut in the eight-way pSeries 660-6M1 last fall.

Sources familiar with IBM's plans say that the pSeries 670 uses a mix of single-core and dual-core Power4s running at 1.1 GHz to create four-way, eight-way, and 16-way SMP servers. These machines span the performance of the current pSeries midrange line, which is based on S-Star processors and ranges from the pSeries 620 up to the pSeries 680.

It looks like the 16-way version of the pSeries 670 uses eight dual-core Power4 chips. The four-way pSeries 670 uses four single-core Power4 (recycled half-duds, effectively). The eight-way uses four dual- core Power4 chips. The only reason anyone cares about the core count is that L2 and L3 cache is allocated on a per-chip basis (not per core). The entry pSeries 670 machines see a 5 to 7 percent bump in processing power because a single core gets all the L2 and L3 cache memory to itself, say my sources.

A 16-way pSeries 670, a 16-way pSeries 690, and a 32-way pSeries 690 Regatta server all support 16 logical partitions; exactly why only 16 partitions are supported on these machines is unclear. The four-way pSeries 670 supports four partitions, and the eight-way supports eight partitions. Partitions are allocated based on the number of cores, but AIX currently only handles a maximum of 16 at the moment. It will very soon be 32, to match the number of processors, and soon after that IBM will offer the fractional partitioning in AIX that is already available on the iSeries line.

For those of you who track code-names, my guess is that all of these pSeries 670 machines are the so-called "Regatta-M" servers (with M standing for "medium" or "midrange," depending on who you ask), and that the four-way and eight-way machines have dual-core Power4 chips.

The pSeries 690, or Regatta-H server (with H standing for "high-end" or "heavy"), was announced last October and started shipping in December. These machines use 1.3 GHz Power4 processors with two cores each to create a 16-way and 32-way commercial enterprise server. Special eight-way and 16-way versions of the Power4 dual-core chips are used to create server nodes for high-performance computing, or HPC, supercomputer clusters. The Regatta-L machines (with L standing for "light" or "low end") will probably debut later this year or early next year, and will very likely offer uniprocessor, two-way, and four-way configurations using stripped-down, single-core Power4s.

The Regatta-L, Regatta-M, and Regatta-H servers are probably very similar to the iSeries Regatta machine that will debut sometime this year, apparently as the iSeries Models 52L, 52M, and 52H. Low-end iSeries customers, knowing that a new architecture of servers was coming down the pike, have apparently expressed a desire to know that the Model 270 machines they buy today will be upgradeable to future iSeries machines. In mid-February, IBM announced to customers that in the second half of 2002 it would offer an upgrade to Model 270 customers. IBM's statement was pretty vague, and I concluded that it seemed very likely that IBM would roll out Model 270 servers using its 668 MHz and 750 MHz S-Star processors.

I didn't know it at the time, but what IBM was telling its sales reps and business partners was that it would offer upgrades from the Model 270 into a future eServer product. In IBMese, that means a whole new machine, and it also means that the odds are that the Model 270 will be upgradeable to the iSeries Regatta- L servers, which may be called the Model 52L. None of this means that faster S-Star Model 270s won't be announced as well. The main reason anyone should care whether any iSeries is an S-Star or Power4 box is that the Power4s have more sophisticated partitioning, resiliency, and diagnostic features built into their electronics, not to mention higher clock speed, more bandwidth, and bigger memories. Dollar for dollar and CPW for CPW, customers should prefer a Power4 server over an S-Star server, provided they don't mind being on the bleeding edge.

On last thing: There are apparently some rumblings in the Somers, New York, and Rochester, Minnesota, offices of IBM's MidMarket Server Division about exactly when to announce the iSeries Regattas. If IBM can move up the pSeries 670 announcement by five months, odds are that it is getting enough yields on the Power4 chips to move up the iSeries Regatta announcements, too. The last hard data I heard about the iSeries Regatta and OS/400 V5R2 announcement is that it is coming on July 23, but this might have changed already. IBM has long-since frozen development on OS/400 V5R2, the version of OS/400 that was slated for the Regattas, and has finished several builds of the operating system with substantial patches woven into it. OS/400 V5R2 does not appear to be ready, while the iSeries Regatta hardware does. If OS/400 V5R1 can be equipped with PTFs that allow it to run on the Regatta hardware, which is almost certainly the case, IBM might decide to do an iSeries Regatta hardware announcement in May or June and leave OS/400 V5R2 until later in the year, when it is also expected to deliver its Domino 6 messaging, collaboration, and workflow middleware.