The Four Hundred

If there is one thing that remains consistent about the IT industry, it is that the day a vendor announces a hot new technology is when companies want to know what the future has in store for them. IBM is not set to start shipping Power4-based servers in the iSeries line until two weeks from now, and customers are already wanting to know what IBM has in store for them with the future Power line of 64-bit RISC servers.

The details about the future Power5 and Power6 processors are sketchy, but IBM wants to calm customers who quite correctly question IBM's commitment to making its own processors in a world where 85 to 90 percent of the processors sold have an Intel processor in them. Only by leaning on IBM for clear future product roadmaps can customers get the commitments from Big Blue that will make them comfortable with the investments they are making in today's eServer technologies. The fact of the matter is that IBM is starting to tell people that it has Power5 and Power6 on the roadmap, which means IBM has development underway for at least two more generations of Power-based servers that will ship between now and 2007 or 2008. That's about as far out as anyone can plan, in all honesty, and this should be something of a comfort.

IBM has been shipping Power4 chips for a few months in the pSeries 670 and pSeries 690 Unix server lines, and will start shipping them in the high-end iSeries Model 890 on June 14 in limited quantities and later this summer in volume quantities. (My guess is that volume quantities for the Model 890 is what amounts to volume quantities. The Model 890 is a very powerful computer, and there just are not that many iSeries shops that need that machine, and even fewer that want to take V5R2 into production that early.) My sources at IBM tell me that Big Blue is getting ready to ship the 1,000th pSeries Regatta server, which is a very healthy run rate for this box. IBM is benefiting from the fact that its largest supercomputer users, who have traditionally bought RS/6000 PowerParallel SP clusters, are not using the pSeries Regatta machines as nodes in clusters. This is yet another example of IBM's consolidating eServer product line, and one that many people forget. The pSeries 690 machines have sold like hotcakes into the high-performance computing market because of their superior bandwidth and number-crunching abilities. The iSeries will ride on those coattails, just like the RS/6000 SPs have.

The Power4 processors used in the pSeries line come in 1.1 GHz and 1.3 GHz clock speeds. The I-Star and S-Star PowerPC processors used in the remainder of the iSeries line run at 500 MHz, 540 MHz, and 600 MHz; S-Stars are available in the pSeries line (and will very likely one day be available in the iSeries line) running at 668 MHz and 750 MHz. IBM's Power processor roadmaps are vague, and intentionally so, to give it wiggle room. Processor designers think in terms of cycle times, which are the inverse of clock speeds. The roadmaps I have seen say that the S-Stars have a processor cycle time (meaning how long it takes to do one cycle on the clock) of 1.6 nanoseconds, which is half as fast as the Power4 processors, which have a cycle time of 0.8 nanoseconds. These nanosecond ratings are very general, since the S-Stars really run at between 1.85 nanoseconds and 1.33 nanoseconds, and the initial Power4 chips run at between 0.91 and 0.77 nanoseconds.

The reason I am getting picky about this is that, when IBM's Power roadmap says that the Power5 processors, due sometime in late 2004 or early 2005 in the "Armada" line of servers, will eventually have a cycle time that is lower than 0.7 nanoseconds, that is a general, not a specific, statement. My best guess is that IBM will try to crest the 2 GHz mark, which would make it roughly equivalent to a 4 GHz Intel Itanium processor. (The Power chip designs have always been much more elegant and efficient than any Intel Pentium or Itanium design. By my own analysis, one clock on a Power chip can do about the same amount of commercial computing work as two clocks on any Intel chip.) I think that initial Power5 processors will run in the 1.9 GHz to 2.1 GHz range, if IBM can pull it off.

IBM has said for quite some time that it plans to deliver a kicker to the current Power4 machines in the pSeries line in October 2002. The Power4-II processors are expected to debut with AIX 5L 5.3, a version of IBM's Unix operating system that has support for truly dynamic logical partitioning akin to that provided in the iSeries line for the past year. The Power4-IIs, which I expect to run at 1.5 GHz to 1.6 GHz, will be available in 16-way Regatta chassis, yielding an effective 32-way server at the top end, because the Power4 chip has two processor cores united by a shared L1/L2 cache on a single piece of silicon. The Power4-II versions of the Regatta machines will support 384 GB of main memory (up from 256 GB with the pSeries 690 and iSeries 890 servers) and up to 100 TB of disk capacity (up from 36 TB in these machines). The denser memory is no big deal, neither is the increased disk capacity. My guess is that this increased disk capacity will come by virtue of moving from the current 36 GB disks to either 73 GB or 147 GB disk drives, the latter probably supplied by Seagate Technology.

Exactly when the iSeries line will get the Power4-II versions of the Regatta machines is unclear, but it could be anywhere from six to nine months after they appear in the pSeries line. That might mean an April, May, or June 2003 announcement for the next refresh of the iSeries line, presumably bringing Power4 and Power4-II processors across the iSeries line, and possibly refreshing entry iSeries machines with faster S-Star processors. Keep in mind that IBM has said nothing officially about what it will do with anything but the largest iSeries server. IBM likes to keep something for announcement day, and it wants to keep its options open so it can react to the fluctuation in supply and demand for Power4 and Power4-II processors across the pSeries and iSeries line. In any event, an iSeries 8XX machine with a 1.5 GHz Power4-II processor should have a rating of about 43,200 CPWs compared with the 37,400 CPW rating for the iSeries Model 890 using a 1.3 GHz Power4 processor. If IBM uses a 1.6 GHz Power4-II processor, that future 32-way iSeries 8XX machine could hit 46,000 CPWs.

The Armada servers will probably debut in October 2004, in the pSeries line running AIX 5L 5.4. IBM sources have said that it will double the number of processors in the top-end Armada servers to 64, from the 32 processors in the biggest Regatta machine. IBM sources have also said that the Power5 machines will support 512 GB of main memory and 200 TB of disk capacity. I think that IBM will hit around 2 GHz for these Power5 processors, but figuring the CPW throughput of these machines is a bit tricky. The aggregate capacity in the top-end box will depend on what technologies IBM employs to get to 64 processors in a single frame.

IBM could, for instance, boost the symmetric multiprocessing capabilities of the underlying Armada chassis to 32-way, from the 16-way symmetric-multiprocessing Regatta chassis. IBM has a few years' experience building 16-way servers across its zSeries, pSeries, iSeries, and soon xSeries lines, but it has never built a 32-way server. (Remember, the iSeries Model 890 is really a 16-way server, with each processor chip having two processor cores.) Sun Microsystems and Hewlett-Packard (both HP proper and its Compaq acquisition) have years of experience building 32-way symmetric multiprocessing machines, and Sun even has 64-way and 72-way symmetric multiprocessing. It is hard to say how efficient IBM's symmetric multiprocessing clustering would be if the Armada chassis were built on expanding the symmetric multiprocessing scalability of the Regatta box.

IBM could also, for the Armadas, double up the number of processing elements on a Power chip complex from two cores on the Power4s to four cores on the Power5s. The Armada chassis would then simply need to be a higher-bandwidth version of the existing Regatta chassis to keep the 64 2 GHz Power5 processors fed. IBM may or may not do this. But what is clear is that the performance characteristics of this four-core, 16-way Armada machine would be different from the two-core, 32-way machine envisioned above.

And, finally, IBM could pull a whole different technology out of its bag of tricks, like Intel just did with its Pentium 4 Xeon server and workstation processors. These Intel chips use a relatively established but unused technology called simultaneous multi-threading, which Intel has renamed Hyper-Threading so it can sound clever. Simultaneous multi-threading virtualizes the instruction pipelines that a processor allows the chip to rejigger them so a single processor chip looks like two processors, at least as far as an operating system is concerned. simultaneous multi-threading was invented for supercomputers in the 1960s and is only now catching on in commercial processors. Simultaneous multi-threading can make a processor do more work than it would otherwise do--not as much as two actual, distinct processors, of course--and exactly how much more will depend to a large extent on how an operating system and its applications were written to take advantage of multithreading in the first place. Intel says that four-way servers using the future "Gallatin" Pentium 4 Xeon processors (due later this year, running at 1.6 GHz and with Hyper-Threading) can do about 65 percent more commercial computing work than a four-way server using 900 MHz Pentium III Xeons. Clock for clock within the same Pentium 4 Xeon architecture, about 15 to 30 percent of the performance gains that customers will see out there in the real world will come from Hyper-Threading, says Intel.

My guess is that IBM will get to 64 processors in the iSeries and pSeries lines by using simultaneous multi-threading, and that it will do a better job than Intel. This is easier in some respects than trying to actually create 32-way servers that run efficiently. If IBM could have done that well, it would have done it by now. Using simultaneous multi-threading is also a more elegant solution to the problem. I think that an iSeries Armada server built using 2 GHz Power5 chips, and using simultaneous multi-threading on a 16-way chassis, should have at least twice the performance of the current iSeries Model 890, or about 75,000 CPWs. If IBM goes for a 32-way symmetric multiprocessing configuration with dual-core Power5s or a 16-way symmetric multiprocessing configuration with four-core Power5s, performance could approach 100,000 CPWs, if Big Blue can get good symmetric multiprocessing efficiencies, but I think this would be very expensive development and would not yield good scalability on all workloads. Keeping processor count as low as possible is always a good thing, whether you are talking server scalability or software pricing.