IBM's Power6 Gets First Silicon as Power5+ Looms
by Timothy Prickett Morgan
The word on the street is that IBM last month achieved first silicon on its forthcoming Power6 chip, due in servers perhaps in late 2006 and maybe in early 2007, just as it is getting ready to ship a kicker to the current Power5, appropriately called the Power5+ chip. The rumors have it that Big Blue is getting ready to launch the Power5+ in its pSeries AIX-based server line in September or October, which is consistent with past announcements and customer expectations.
IBM refused to comment on the veracity of these rumors, as is the traditional stance of all IT vendors when it comes to rumors about the timing and technical features of future products--excepting their own statements and roadmaps, of course.
Various high-level sources at IBM were very clear in late 2004, and again in early 2005, that the iSeries line of servers, also based on the "Squadron" server design and the Power5 processors, like the pSeries line of machines, would not be upgraded to Power5+ processors in 2005. While IBM has not said why this is the case, it is not hard to surmise. The Power5+ chips will be using a new 90 nanometer chip-making process, and the yields will not be particularly high. Every one of them that comes off the line working properly will be precious, and will be delivered to customers who need the absolute best raw performance that IBM can bring to bear in the server market. IBM has direct competition in the Unix market, and Power5+ is really aimed at these customers. To put it bluntly, in terms of green-screen performance, the iSeries line was overkill for most customers back in the late 1990s with the S-Star and I-Star processor lines, so the Power5+ must be a nuclear holocaust or something (to take a bad analogy and make it worse, with my apologies to Paul McCartney on that parenthetical).
The Power5+ chip will be a shrink of the current Power5 chip, which is based on a 130 nanometer, copper/SOI process used first in the 1.7 GHz Power4+ chip that came out in July 2003 and was subsequently used to create the 1.9 GHz Power4+ in February 2004. With the Power5+ chips, IBM is moving to a 90 nanometer copper/SOI process, a very similar process that is being used by IBM to create the "Cell" PowerPC processor that will be used by Sony and Toshiba in various electronic devices. While IBM will probably implement some circuitry changes in the Power5+ chip, the rumor is that there will be no significant changes to the cores in the processors. IBM could possibly increase the size of the on-chip L2 cache, which is shared by both cores in the Power4 and Power5 families of chips. For instance, when IBM moved from the Power4 to the Power4+ chip, it increased the size of that shared L2 cache to 1.9 MB from 1.4 MB. IBM could tweak other things here and there, but the Power5+ chip should plug into existing Squadron machines; most server designs are created to handle at least two generations of processors.
It would be interesting if IBM could boost the logical partitioning capabilities of the Squadron platform with the Power5+ chips, perhaps doubling from the current 10 partitions per processor core to 20 partitions--or even higher. With anywhere between 30 and 60 percent higher performance (comparing a 1.9 GHz Power5 chip to a 2.5 GHz or 3 GHz Power5+ chip), there should be room to do this. Many customers would love to support more than 254 partitions on a big Squadron box, and frankly, it might even make sense for IBM to quadruple this and really go after big server consolidation jobs.
The main benefits of the Power5+ chip should be much lower power consumption and heat dissipation in the same clock speed range, as well as more performance in about the same heat range. The Power5 processors run at 1.5 GHz, 1.65 GHz, and 1.9 GHz (with the two lower speeds available in the iSeries line and the top-end speed only available in pSeries machines where the extra performance is critical). As I have said before, because of the differing performance and heat constraints of the server market, I think IBM will probably offer a wider variety of clock speeds for the Power5+ generation, allowing customers to push up into the 2.5 GHz to 3 GHz range for machines with about the same CPU thermals and maybe even down into the 1.5 GHz range or a little lower for customers who want about the performance as the Power5s, but with half or less of the power consumption and heat dissipation.
If IBM doesn't offer customers options that trade off compute power and heat, it is being silly; this is what its main competitors in server processors--Intel and AMD--are doing. Such a chip, running at as little as 1 GHz, would make a nice entry iSeries processor. IBM, if you have a lot of duds that don't run at 2.5 GHz, make some puppy iSeries boxes out of them--don't throw them in the trash.
Moreover, offering a low-speed, low-heat Power5+ would allow IBM to create a very powerful hybrid AIX/Linux workstation. HP and Sun have let their Unix workstation lines languish--HP withdrew support of HP-UX on Itanium workstations last summer, in fact. So there is a chance to go after flops-hungry workstation customers with Power5+ as well. But IBM may not go for this opportunity if Power5+ yields are not high. Considering the trouble IBM's Microelectronics Division had getting its 90 nanometer processes online--and one of the reasons why it has lost Apple as a chip customer--it is hard to believe that IBM will have the chip volumes to do pSeries servers with Power5+ in 2005, and then maybe add some iSeries servers in 2006 (perhaps when i5/OS V5R4 debuts sometime next year), and then do maybe 10 times the volume of these servers in Unix/Linux workstations using Power5. But, if it could get yields on 90 nanometer for Apple (eventually), maybe it can get yields for a workstation line, too.
Power6: To ECLipz or Not to ECLipz
There is a lot of chatter about what Power6 is and isn't and 18 months has not really cleared up the confusion about what IBM future Power6 processor is and isn't. IBM finished up the design of the chip earlier this year (prior to March, and I am not sure when) and did what is called a "tape out," which means the data that describes the process by which you make the masks to make the chips is finished and sent to the chip factory (also called a fab) so they can start making the chips. When the first chips that function come off the assembly lines at the factory (in this case, IBM's 90 nanometer, 300mm wafer facility in East Fishkill, New York), this is called "first silicon." According to my sources, the Power6 went into first silicon sometime in July, and IBM has actually put the chips into test systems. Those sources say that IBM has booted the open source Linux operating system on the Power6 chips, but has not yet put the AIX or i5/OS operating systems on them.
The Power chip roadmaps from a few years ago caused some confusion in that they indicated that IBM would be using a 65 nanometer process for these chips, due in 2006 and 2007, and could be ramping clock speeds up as high as 6 GHz. The roadmap characterized the clock speeds on the Power6 chips as "ultra high frequency," and unlike the Power4, Power5, and Power5+ chips on the roadmap, the Power6 item did not show two cores, but simply an area that said "cores," plural. It also said "L2 caches," and said "Advanced System Features" instead of the distributed switch that occupies two sides of every Power4, Power4+, Power5, and Power5+ chip. This distributed switch is the high-speed interconnection that allows four dual-core Power chips to be lashed together into an eight-way SMP server inside a multichip module (MCM), which is a single piece of electronics that is about as big as the palm of your hand. This MCM also contains the L3 caches. To make a big SMP box, like the 64-way Squadron i5 595 and p5 595 machines, you put eight of these eight-core MCMs on cell boards (which IBM calls books) and you have made a big, bad box.
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