The Four Hundred

The Hot Chips conference took place last week at Stanford University and IBM raised the curtain a little on its forthcoming Power5 processor. While we have already divulged many of the details on the Power5 chips, which are due in the second quarter of 2004, this was the first time IBM publicly talked about them.

Ron Kalla, a senior staff member on IBM's Power chip design team, is today giving a demonstration at Hot Chips where he will talk about the architectural changes that IBM is making with the Power5 chips to add simultaneous multithreading (SMT) to the chips. He will also talk about some of the innovative power management features that IBM has woven into the Power5 chips that will allow it to consume less electricity and generate less heat.

While most people don't know this, prior generations of IBM's 64-bit PowerPC processors--specifically the "Northstar," "I-Star," and "S-Star" processors--implemented a version of hardware multithreading, a kind of rudimentary version of SMT that allowed one physical processor to look like two virtual ones to an operating system and its applications. With the "Spinnaker" Power4 and Power4+ processors, IBM put two single-threaded cores on a single die and concentrated on driving up the clock speed to push performance. With the Power5 and Power5+ processors, which will ship in a line of machines dubbed internally at IBM as the "Squadron" line, IBM will mix a much more sophisticated hardware multithreading (which will support two threads per core) with the chip multithreading of the Power4 and Power4+ (which is just a fancy way of saying dual cores with a shared L2 cache on a single chip) to make a much more efficient superscalar processor.

According to Mark Papermaster, director of microprocessors at IBM's Enterprise Systems Group, Big Blue spent a great deal of time studying what it would take to make a more efficient SMT implementation. Right now, the only widely used, commercial implementation of SMT is Intel's HyperThreading in the Xeon DP and MP processors for servers and workstations. The HyperThreading gives multithreaded applications like Web servers and database servers two virtual processors to play with for each real processor, but performance improvements due explicitly to HyperThreading was initially pegged at 25 to 30 percent. This is a big improvement, and means that Intel can keep clock speeds down for some workloads and therefore not sacrifice performance. A lot depends on how applications are written. Big monolithic, single-threaded, homegrown applications--like the kind in use in corporations around the world--are not going to see any improvement from HyperThreading, SMT, or any other name you want to give it.

While not committing to any performance benefits specifically attributable to SMT on the Power5, Papermaster did say that he expected that IBM's implementation of SMT would be the best in the industry. If Intel can get 25 to 30 percent, maybe IBM can get 35 to 40 percent. Maybe it can do a little better than that. The changes that IBM has made to the Power5 chip suggest that architecturally it does have an edge over the Xeon processors. First, the Power5 chip will have a sufficient number of registers to keep its virtual pipelines fuller. Moreover, the execution units in the Power5 cores have duplicate control circuitry so they can better handle multiple virtual streams. IBM is also moving main memory closer to the processor by putting the main memory controller on the chip itself. Papermaster once again reiterated IBM's claim that the Squadron servers would deliver four times the performance of the original Power4 "Regatta" servers that started rolling out in October 2001 at the high-end of IBM's Unix server line.

The other interesting feature of the Power5 that IBM talked about at Hot Chips is dynamic power management. With the Power5, IBM has added circuitry to the processor that allows elements of the chip that are not being used by the applications on a server or workstation to be quiesced. Rather than just shutting down a whole core, L2 cache, or data switch on a Power5 chip, IBM's dynamic power management can shut down pieces of a core, cache, or switch that are not being used. When the applications call for more computing power, the chip fires up the transistors. In this way, a Power5 chip will use less electricity and only get as hot as need be based on the workloads actually running on the Squadron server. Considering how hot a multiple-gigahertz processor from any vendor is these days, this innovation will be welcomed by IBM's customers--particularly since it all takes place inside the Power5 chip and operating systems and applications do not need hooks to make use of this.

Here's what else is known about the Power5, and which IBM probably will not talk about at Hot Chips. The initial Power5 processors will be implemented in the same 130 nanometer copper/SOI process used to create the 1.2 GHz and 1.45 GHz Power4+ processors. The word on the street is that clock speeds will range from 1.5 GHz to 2 GHz or higher with the Power5s. The Power5+ processors, due sometime in 2005, will use a 90 nanometer copper/SOI process and could scale from 2 GHz to 3 GHz or faster. These Power5 and Power5+ chips will be manufactured in IBM's most advanced 300mm fab line in East Fishkill, New York.

The Power5 and Power5+ chips are dual-core processors with a shared L2 cache memory and external L3 caches integrated on multichip modules (MCMs). The Power4 MCMs had 1.44 MB of L2 cache, and the Power4+ chips have 1.5 MB of L2 cache on each dual-core chip. With the Power5 chips, IBM will jack up the size of the L2 cache to around 1.9 MB to 2 MB, we hear. The main memory controller and L3 cache controllers will also be put inside the chip, which will reduce latencies and speed up throughput. Power4 and Power4+ chips had external L3 caches and only a memory look up table (rather than the full controller) is on the chip. This eight-way Power5 MCM will support 64 GB of main memory, up from 32 GB with the Power4 machines, yielding support for 512 GB of main memory. IBM could double this main memory support if there is market demand for it. The Power5 chips support SMT and will scale to 64-way symmetric multiprocessing (SMP). IBM is expected to make enhancements in the electronics in the Power5 chip to accelerate floating point operations as well, but what these enhancements might be is unclear.

We have also heard that IBM is planning to put some extra database and networking acceleration chips into the Power5 MCMs to speed up common commercial workloads. IBM could use some derivative of the PowerPC design for this work, perhaps an embedded PowerPC chip or maybe the new PowerPC 970 "G5" chips IBM makes for Apple Computer for its desktops and servers. Everything that an auxiliary processor in the MCM can do to speed up database work leaves more work for the main processors in the Squadron complex to do.

It appears that there will be two flavors of the Squadron machines. One set, which we hear will be announced in the second quarter, will scale from two to eight processors. Another set of machines will scale from eight to 64 processors. These will be delivered later. While the high-end got the Power4 processors first, the midrange got the Power4+ chips first and the midrange will get the Power5+ chips first this time around, too.

The Squadron servers will come with pSeries brands supporting AIX and Linux and iSeries brands supporting OS/400, AIX, and Linux. There is always talk of a consolidated Power brand, and this could yet happen. IBM certainly won't talk about it. But it makes a certain amount of sense to have a united pSeries/iSeries line with a single sales force and a single set of prices. However, IBM is able to wring profits out of the iSeries base by pretending that the iSeries hardware is not the same as that used in the pSeries line and therefore charging OS/400 shops more money for memory, disks, and processors. So unless IBM has lost its mind, thinks it needs to have parity on iSeries and pSeries hardware, or knows that iSeries profits are nil except on the OS/400 and related systems software (and hence hardware convergence doesn't have any real negative effects), a convergence of brands is not necessarily a foregone conclusion as many IBM watchers and customers think. The odds do not favor it. But a good argument can be made to make a single eServer Power line and be done with it, so it is possible if not probable.