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The i5 Attains Common Criteria EAL 4 Certification

As IBM promised it would, the team at the Rochester labs has been able to put the i5 through the Common Criteria paces and attain the Evaluation Assurance Level 4 (EAL4) certification. This is the first time that the AS/400 or iSeries platform running OS/400 or i5/OS has been put through the Common Criteria certification process, which is an important hurdle to get over for certain financial services and government IT contracts.

The Common Criteria certification is the result of the merging a few years ago of security standards from North American and European governments, and it is used to separate products that have demonstrated their security, as audited by expert third parties, from those products that cannot or have not attained the certification. The Common Criteria certification is different from but similar to the U.S. Department of Defense's Common Operating Environment certification, which is administered by the Defense Information Systems Agency. Back in January 2004, IBM certified Novell's SUSE Linux Enterprise Server 8 running across its entire eServer line (iSeries, pSeries, xSeries, and zSeries) at the EAL3 level, which is sufficient for some government contracts. The EAL ratings do not just apply to servers and operating systems, but other networking gear and middleware applications that are vital to modern computing. You can see the Common Criteria report for the i5 line--IBM certified

IBM certified the i5 520, 550, and 570 on the Common Criteria tests, but not the i5 595 for some reason. You can see the Common Criteria report for the i5 line at http://niap.nist.gov/cc-scheme/st/ST_VID4035-VR.pdf. I went nuts trying to figure out what the special feature of the i5, feature code 1930, was in the configurations that were tested, but this seems to be a bizarre way to simply say i5/OS V5R3. To date, IBM has achieved EAL4 certification on logical partitions running on Power4-based pSeries 630, 650, and 690 servers and on zSeries 800, 900, and 990 mainframes. Sun Microsystems reached EAL 4 on Solaris 8 on its Sparc servers two and a half years ago and on Solaris 9 in January of this year, and Hewlett-Packard hit EAL4 on its PA-RISC servers running HP-UX 11i in September 2001. IBM certified AIX 5L 5.2 at the EAL4 level on its Power4 servers in September 2002 as well. Red Hat is currently working on EAL4 certification on its Enterprise Linux 4 version and presumably Novell is doing the same with SLES 9.

Some More Thoughts on the Future Power6 Chips from IBM

Last week, I told you about how I had heard a rumor that Power5+ processors were imminent in September or October and that IBM had achieved first silicon on the future Power6 processors about a month ago. I went on to speculate a heck of a lot on what the Power6 chips might look like. (You can read that original story by clicking here.

The more I think about Power6, the more I think that the Power6 design will incorporate not just a new cache hierarchy as I described, but dedicated processors for handling special functions and that it will not include more than two Power cores. I am not entirely sure that i5/OS has the software features activated yet, but the Power5 processors incorporate a feature called Fast Path that allows TCP/IP networking, as well as the Message Passing Interface (MPI) protocol used in supercomputing clusters, to be offloaded from the Power cores to specialized circuits. AIX and Linux support these features, and it allows these boxes to do more work than they might otherwise do. IBM could add different circuits to accelerate common routines that bog down the operating system--which is something it can do because it owns OS/400 and AIX and Linux is open source. Mainframes have had hardware-assisted database processing for years, and it seems like a good idea, particularly for the iSeries. Accelerating Java virtual machine functions is probably also a good idea.

A few years back, there was some talk about IBM adding vector processors to augment the already substantial floating point processing capability of the Power chips. (Each Power chip has two cores, each with two floating point units that are each capable of two instructions per clock cycle. That's eight floating point ops per clock per socket, peak performance, which ain't all that shabby.) But as the "Cell" PowerPC hybrid processor that IBM has created in conjunction with Sony and Toshiba demonstrates, such an approach is not only possible, but has been done. The AS/400 was the first asymmetrical processor in the world, using what were essentially modified Motorola 68K processors as its main processors and distributing I/O and other functions to auxiliary processors that were called I/O processors, or IOPs. Such an approach with Power6 would do inside chip packaging what the AS/400 did at the system bus level. Same idea, slightly different implementation.

There is also a slight--ever so slight--possibility that IBM will goose simultaneous multithreading (SMT) with the Power6 chips, perhaps going from two virtual threads per core to four virtual threads per core. IBM's implementation of SMT is delivering 35 to 40 percent performance over a non-SMT cores, which is just stunning when you think of the fact that Intel could only get at best about 20 percent improvement with its SMT implementation, which it calls HyperThreading. Intel's HyperThreading was a boon for marketing and for certain workloads, but not so much for performance on applications with limited threads, and that is why Intel's future chip architecture will not have HyperThreading. However, Sun Microsystems is going the other way with its "Niagara" processors, adding four threads per core and eight cores per chip to create a 32-threaded chip. These Niagara cores--as well as the future "Rock" processor cores--are based on a stripped down UltraSparc-II cores--not UltraSparc-III or UltraSparc-IV. As Thoreau once said, "Simplify." I think there is a very good chance that Power6 may have and Power7 will have many threads per core--maybe four--and maybe two or four cores. By late 2007 or early 2008, software, including operating systems, might be able to take advantage of more threads, whether the come virtually through SMT or through increasing core counts. If IBM can virtualize the threads in the Power6 and Power7 cores again as it did with the initial Power5s using SMT, doubling thread count to four virtual threads per core, it can get one SMT core to do the work of two real, non-SMT cores. That would be a neat trick, indeed.

No matter what IBM does with Power6 and Power7, let me give you some good advice: thread your applications like crazy. Because clock speeds will go down long before they will go much higher than 4 GHz. The thermal ceiling is creating a clock ceiling for processors, and we had all better get used to it.

"Cell" Partners Try to Round Up Support for the Chip

In an effort to try to drum up licensees for the "Cell" derivative of the PowerPC architecture, IBM, Sony, and Toshiba, the three partners who co-developed the Cell chip, have released a flurry of technical specs to explain in detail the chip's architecture, its application binary interfaces, and how its C++ and Assembler compilers work. (If you want to read stuff that is way over my head, take a look at these documents at http://cell.scei.co.jp/e_download.html.) The official name of the architecture is the Cell Broadband Engine Architecture (CBEA), and the three are pitching the Cell chip for game consoles, multimedia devices, and perhaps workstations and clusters for supercomputing jobs.

The 64-bit PowerPC core at the heart of Cell is somewhat simplified in that it does not, like the past many generations of PowerPC and Power processors from IBM, support out-of-order instruction execution. It has 32 KB each of instruction and data cache, a 512 KB L2 cache, and a Rambus XDR memory controller and I/O interface all implemented on the chip. The chip also includes eight synergistic processor units (SPUs), which are in effect vector math co-processors to boost the performance of streaming media and video calculations; they can do integer and floating point math, by the way. The Power core and the SPUs are connected to each other through a high-bandwidth element interconnect bus (EIB). Multiple Cell chips can be glued together to create compute clusters.

A single Cell chip has 235 million transistors, but thanks to the 90 SOI nanometer process IBM is using to make it, only cranks out about 80 watts as it delivers 256 gigaflops of number-crunching power when it runs at about 4 GHz and at 1.2 volts. Cutting the clock speed back to 3 GHz could drop the voltage and the heat way back--maybe as low as 50 to 60 watts running at 0.9 watts, but still delivering 192 gigaflops.

The question is this: What can you do with a Cell chip? Well, it would make a very good encryption co-processor or a special co-processor for handling any streaming media, that is for sure. There are undoubtedly other possibilities. Like running OS/400 natively on it and using the vector units to somehow goose database performance. But the chip may not have support for the special memory tags that OS/400 requires. This is still unclear.

Sirius Invests Over $1 Million on Three Innovation Centers

Sirius Computer Solutions, the server reseller based in San Antonio, has fought tooth-and-nail with competitors to become the largest reseller of IBM server gear in the world. Having gotten there, Sirius intends to stay there, and to that end, the company has sunk over $1 million in into opening three new Business Partner Innovation Centers, located in Denver, Colo.; Portland, Ore.; and Dallas, Texas. The centers are intended to showcase new technologies and to allow software developers and end-user customers who partner with Sirius to modernize their applications and infrastructure. Some 250 Sirius consultants work with partners and customers to give them access to the centers, which provide on-site and remote usage with Web cameras.

Lakeview Partners with Innovatum for Compliance, Auditing

iSeries high availability software vendor Lakeview Technology said last week that it has signed a partnership deal with Innovatum, an IT consulting and software development company that has created applications that are of growing importance in the age of IT compliance.

Innovatum has one product suite called ROBAR, which is used to print barcodes and track inventory for companies that are regulated by the Food and Drug Agency in the United States. The company has another package called DataThread, which is data audit and workflow middleware that hooks into applications and delivers the technical remediation requirements of regulations such as SOX, HIPAA, FDA CFR part 11, and Gramm-Leach-Bliley. (If you know what any two of those are, you probably work in a modern corporation.) Innovatum also sells an RFID management tool called ROPICS, which hooks RFID tracking systems into ERP software systems.

Lakeview, of course, sells high availability clustering and data protection software for OS/400, Unix, Windows, and Linux platforms. And while many regulations do not require high availability software, the spirit of the law clearly makes high availability clustering of production applications a relatively easy way to get compliant in certain ways. So marrying the Lakeview and Innovatum applications is probably a good way for both companies to pursue more business.

Infor Buys PLM Software Provider Formation Systems

Only a few weeks ago, our sister newsletter, Four Hundred Stuff, had a report on how Infor Global Solutions has grown by acquiring a whole bunch of software providers, notably MAPICS, daly.commerce, Brain, and Lilly Software. (See Infor Taking an 'Assembler' Approach to ERP Acquisitions And last week, the company was at it again, acquiring Formation Systems, a specialist in product development optimization. Infor, a private company backed by venture capitalist Golden Gate Capital, did not disclose the details of the acquisition.

Formation Systems, which is based in Southborough, Mass., will be merged into the process manufacturing group at Infor. Technically, the Optiva suite created by Formation Systems a product lifecycle management (PLM) application designed specifically for process manufacturers, who make beverages and other liquid foods, cosmetics and health products, specialty chemicals, and paint. Just like modern ERP software covers all aspects of manufacturing--from the supply chain of parts, to manufacturing of the product, to sales, distribution, and customer support--the Optiva software manages the development of new products from conception to prototype development on to the point where the products are actually made. And like ERP software, the PLM software hooks into the supply chain, so you can design a product with the economics and parts availability of that supply chain in mind from day one. In the case of process manufacturers, this means creating formulas and recipes.

Zotob Removal Tool Available From Microsoft

An updated version of Microsoft's Malicious Software Removal Tool that zaps the Zotob worm from infected Windows 2000 computers was released last week by the vendor following several high-profile outbreaks (see "Windows 2000 Worm Wreaks Havoc").

Despite the decidedly negative impact that Zotob had on CNN (which struggled to put the Lou Dobbs Tonight broadcast together manually after some of its production systems were brought down by the worm) and the San Diego County government (whose 12,000 Windows 2000 computers, handling such things as wedding licenses and building permits, were taken offline for up to a day), Microsoft labeled the worm with a low-severity level, saying that "only a small number of customers have been affected" by the worm. That is certainly true compared to the Blaster and Sasser worms of years past. But not everybody agreed with Microsoft's assessment of the Zotob worm and its many variants, which can spread across networks without requiring a user to open any software or files. Antivirus software vendor McAfee, for one, rated Zotob a "high risk" worm.