The Four Hundred

It was the fall Intel Developer Forum last week, and the bigwigs at Intel assembled the multitudes in San Jose to give them a sneak peak at future processor and related technologies and a view of how they see the world of computing. While the theme of communications-computing convergence that Intel has been talking about for year is interesting, what most people in the enterprise want to know is what Intel is going to do with its processors.

To that end, Paul Otellini, who is president of the company, raised the curtain a bit on future 32-bit Pentium 4 Xeon and 64-bit Itanium processors. He also gave some background on the current and expected adoption rates of specific technologies that Intel thinks are key.

Before discussing the processors themselves, Otellini spoke about the company's hyper-threading technology, which is an implementation of what most of the computer industry refers to as "simultaneous multithreading." Hyper-threading technology takes two instruction pipelines inside of a processor core and rejiggers the streams of instructions inside of them in such a way that the processor can present a view of two virtual cores to the operating system running on that processor, instead of one. Hyper-threading technology can boost performance by a considerable amount: maybe 25 to 30 percent on certain workloads. Hyper-threading technology only costs a little, in terms of transistor count, and it boosts performance without the need to boost clock speed. This cuts down on the electricity that a chip needs to operate and the heat that it dissipates. It is no surprise, then, that Intel has been weaving hyper-threading technology into its processors as fast as it can.

Otellini said that Intel has implemented hyper-threading technology in the current Xeon DP and MP processors for two- and four-way or larger servers. By the end of the year, he estimates, the use of chips with hyper-threading technology will exceed 50 percent of the "performance desktops" that Intel's partners sell using its chips, and he predicted further that hyper-threading technology would be "pervasive" by the end of next year, by which he means, presumably, that all new laptops, desktops, and servers selling would have hyper-threading technology inside of their Intel chips. While the Itanium processors do not yet have hyper-threading technology embedded in them, the obvious benefit to performance that hyper-threading technology would bring, particularly to multithreaded applications like Web servers and databases, means that Intel is clearly working on this.

While hyper-threading technology can help boost performance by presenting two virtual cores to an operating system and its application for every one real core, performance can also be boosted by putting multiple cores on a single chip. IBM has already done this with its Power4 processor, and Hewlett-Packard and Sun Microsystems are working on dual-core processors with their respective PA-8800 and UltraSparc-IV processors, which are due near the end of this year or early next year. Earlier this year, Intel committed to bringing out the dual-core implementation of the Itanium processor, code-named "Montecito," sometime in 2005.

At the Intel Developer Forum, Otellini said that the "Tanglewood" implementation of the Itanium processor (which will come to market sometime after Montecito) will have "multiple" cores, which probably means four, but it could mean six or even eight, depending on how ambitious Intel wants to be and where various chip-making processes are in terms of yields. The Tanglewood chip is being designed by Intel Itanium engineers, as well as a team of chip designers from the former Compaq (well, actually, the former Digital Equipment) who were working on the EV8 and EV9 versions of the Alpha processor before Compaq shuttered that business and sold off the intellectual property for Alpha, along with the people who worked on it, to Intel. All that Otellini would say about Tanglewood, besides that it exists and is being designed by this hybrid Itanium-Alpha team, is that it would deliver seven times the performance of the current 1.5 GHz "Madison" implementation of Itanium.

What might such a chip look like? It is hard to say, but let's take a stab at it. Say you added hyper-threading technology to the Madison core and made four cores share a single L3 cache of 6 MB capacity. If you could do that with Madison today running at 1.5 GHz, each Madison core would perform like a 2 GHz core on multithreaded applications just because of the hyper-threading technology. Making the four cores share that L3 cache on-chip would present some overhead, just like symmetric multiprocessing does on servers, but maybe a four-core Madison might deliver 65 to 75 percent of the aggregate performance of those four processors where the rubber hits the road. When you combine the effects of hyper-threading technology and multiple cores, a 1.5 GHz version of the four-core Madison would deliver about the same performance as a single Madison core running at 5.46 GHz. If you could jack up the clock speed on this theoretical device to 3 GHz, it would have about 7.3 times the performance as a 1.5 GHz single-core Madison.

On the 32-bit front, Otellini also talked a little bit about the future Xeon processors dubbed "Potomac" and "Tulsa."

Intel already talked about some of the chipsets for these machines back in June. In 2004, Intel is planning to introduce the "Lindenhurst" chipset, for future Xeon DP processors for two-way workstations and servers, and the "Twin Castle" chipset, for future Xeon MP processors for four-way servers. These two chipsets will incorporate support for PCI Express point-to-point I/O interconnections and will also support DDR2 memory subsystems. The Lindenhurst chipset is expected to be matched with the future "Jayhawk" Xeon DP processor in the second half of 2004, while the Twin Castle chipset will work with the future Gallatin chips with 4 MB integrated L3 cache, due in early 2004, and the "Potomac" Xeon MP chips, due in the second half of 2004.

Otellini didn't talk at all about the Jayhawk Xeon DP processor, and he did not get into specifics about Potomac other than mentioning it as the future Xeon MP processor. He didn't say much about the Tulsa Xeon processor, either, except to say that it would be a dual-core implementation of the Pentium 4 Xeon processor and that it would include hyper-threading technology, as all the Xeons now do. The word on the street is that it will take Intel two to three years to actually get Tulsa out the door. That puts it anywhere from concurrent with Intel's first 64-bit dual-core chip, the Montecito Itanium, to a year after it. He said even less about when multiple-core Pentiums and Itaniums might appear for desktop and laptop computers, but he hinted that they would come eventually.

Mike Fister, general manager of Intel's Enterprise Platforms Group, fleshed out the roadmap for the Xeon line a little bit more than Otellini did a few days earlier. Fister's roadmap shows that a "Gallatin" Pentium 4 Xeon MP processor running at 3 GHz and with 4 MB of L3 cache was due in late 2003 or early 2004. The Potomac Xeon MP would have a larger cache and higher clock frequencies enabled by the move to 90 nanometer chip processes. In the Xeon DP line, the current "Prestonia" chips have 1 MB of L3 cache and run at a top speed of 3.06 GHz. The future Nocona Xeon DP chip, due in early 2004, will run at 3.2 GHz and will sport an 800 MHz frontside bus; it will be implemented in a 90 nanometer process as well. The Jayhawk Xeon DP, due in late 2004 or early 2005, will be the same chip but with a higher clock rate. Just how high, Intel is not saying.

One of the cooler new things that Otellini talked about was another virtualization technique called Vanderpool. With Vanderpool technology, Intel is going to weave hardware-based processor partitioning into the future Intel product line. Otellini says that this will happen within the next five years, which is not a very aggressive rollout considering that RISC/Unix servers and proprietary machines have had this virtualization for years.

The talk at the Intel Developer Forum wasn't all that happened on the X86 processor front recently. Two weeks ago, both Intel and Advanced Micro Devices rolled out two new 64-bit processors aimed at the workstation and server markets, to help them better compete against others in the chip market in general and against each other in the X86 market in particular. Both companies are trying to get market momentum behind their respective Itanium and Opteron lines.

The Itanium 2 and Opteron processors have won accolades for many of their technical features and have earned the scorn of some snobby rivals in the RISC/Unix chip business, but the one thing they haven't won so far is a lot of business. But, with each improvement in the Itanium 2 and Opteron lines, Intel and AMD are getting products out the door that are more appealing to commercial customers.

This is particularly true with the new "Deerfield" Itanium 2 processors, which are a trimmed-down version of the "Madison" Itanium 2 chip, which Intel launched at the end of June. (See "Intel Counts on Third Time Charms, Performance with Madison" for full details on the Madison announcement.)

The Madison chip has an improved core design over the first-generation "Merced" Itanium processors, which were late, delivered less performance than many expected, ran very hot, and were therefore not enthusiastically supported by the server and workstation makers of the world. The Madison chip fixed some of these problems, in that it had a very large cache, ran somewhat cooler, and delivered the kind of performance that compared nicely with RISC/Unix alternatives. Intel has three versions of the Madison chip, each with a different price and performance point. The entry Madison chip runs at 1.3 GHz and has 3 MB of L3 cache. It will sell for $1,338 in 1,000 unit quantities. The middle chip is slightly faster, at 1.4 GHz, and has slightly more L3 cache, at 4 MB; it costs $2,247 per 1,000. The fastest Madison chip runs at 1.5 GHz, has 6 MB of L3 cache, and costs $4,426 per 1,000.

The Deerfield variant of the Itanium 2 was designed for denser machines and working conditions where electricity usage and heat dissipation are issues. The Deerfield chip is technically known as the Low Voltage Itanium 2. It runs at 1 GHz and includes only 1.5 MB of integrated L3 cache memory. Like all Itanium 2 chips, it has 32 KB of L1 cache and 256 KB of L2 cache on-chip. The smaller L3 cache and lower clock speed allows the Deerfield chip to top out at 62 watts of power consumption when it is running all-out, which is about half the power of a Madison chip running at 1.5 GHz and with 6 MB of L3 cache. On a lot of workloads, the Deerfield will consume half the watts for two-thirds of the performance--a tradeoff that many customers have asked Intel for. Perhaps more significant, the Deerfield chip only costs $744 in 1,000-unit quantities, which means it delivers four times the bang for the buck over the Madison chip on workloads that do not need that big L3 cache. Uniprocessor workstations and two-way servers are going to be the sweet spot for Deerfield, which stands to reason considering this is its design point.

Just before the Madison launch, we reported that Intel was working on a variant of the Madison processor aimed specifically at high-performance computers used for number-crunching jobs. The high cost and the high heat of the Madison were making it hard for Itanium to gain traction in the high-performance-computing market. (Hewlett-Packard, pitching Itanium, lost the 100 teraflops Red Storm deal to an AMD Opteron cluster proposed by Cray, and it has also lost some big deals to rival IBM, which pushes its Power4 and Power5 RISC/Unix chips.) To make Itanium more attractive to high-performance-computing customers, Intel last week debuted a new Madison chip running at 1.4 GHz and having only 1.5 MB of L3 cache on chip. This new Madison processor has the same 400 MHz, 128-bit system bus as all the other Itanium 2 processors (including the Deerfield), and supports 6.4 GB/sec of memory bandwidth. On computationally intensive workloads, such as those simulating hurricanes as they move toward the East Coast, the new high-performance-computing variant of Madison will deliver about 90 percent of the performance of the biggest, baddest 1.5 GHz Madison, but because the cache is 25 percent the size, it will consume a lot less power. At $1,172 in 1,000-unit quantities, it delivers a factor 3.5 improvement in price/performance compared with the top-end Madison processors.

AMD is continuing to flesh out its 64-bit "SledgeHammer" Opteron processors, which can support 32-bit and 64-bit modes at the same time. (The Itanium processors run a new 64-bit instruction set that is unique from the X86 instruction set used in the 32-bit Pentium family. The Itaniums do have an X86 emulation mode, but it does not offer very good performance. Intel is working on that.) Back in April, AMD debuted the Opteron in three different versions: one for uniprocessor machines (the 100 series), one for two-way servers (the 200 series), and one for four-way or eight-way servers (the 800 series). The initial Opterons ran at 1.4 GHz, 1.6 GHz, and 1.8 GHz; they include 128 KB of L2 cache and 1 MB of on-chip L2 cache. The Opteron design also includes an on-chip DDR-SDRAM memory controller--an industry first and the source of many performance benefits. This allows the memory controller to run at the same core frequency as the Opteron processor. (Off-chip memory controllers typically run at half the speed or slower.) And with each chip having its own memory controller, memory bandwidth scales as Opterons are added to a processor complex. Each processor can have eight DIMMS, and that means 8 GB of main memory per processor using today's DRR-SDRAM technology. That gives an eight-way Opteron box 64 GB of main memory and 5.3 GB/sec of memory bandwidth to play with.

Two weeks ago, AMD rolled out the Opteron 146, a 2 GHz chip for uniprocessor machines, which it is selling for $669 apiece in 1,000-unit quantities. AMD also has rolled out a 2 GHz Opteron 246, which it will sell for $3,199. This pricing delivers performance akin to Intel's 32-bit Pentium 4 Xeon processors plus 64-bit support (like Itaniums have) at prices that are absolutely competitive with Xeons.

While IBM has come forward and is supporting the AMD 246 processors in its eServer 325 line, no big server vendor has stepped forward and said that it would deliver a full set of workstation and server products that use the AMD Opterons as their main processors. If AMD wants to compete against Intel's Itanium, it is going to have to rally more support. None of the major server vendors has a vested interest in undermining their own RISC/Unix lines, and HP, which has put all of its server eggs in the Itanium basket, wants nothing to do with Opteron. This is a quandary for AMD, which has designed a great processor that no one will use except in precise and limited markets--at least for now.

Finally, last week AMD debuted the "ClawHammer" variant of the 64-bit Hammer chip, which is being sold as the Athlon 64. This chip is basically a stripped-down Opteron designed for desktops and workstations, but it will probably also end up in entry servers and maybe even Linux clusters. AMD is selling a special version of this chip called the Athlon 64 FX for gamer PCs ($733 each for quantities of 1,000); it runs at 2.2 GHz, has 1 MB of L2 cache, one HyperTransport port, and a 128-bit memory controller. Another version is called the Athlon 64 3000+, which runs at 2 GHz and has 1 MB of L2 cache and a 64-bit memory controller. This chip is aimed at notebooks and costs $278 apiece in 1,000 quantities. The third ClawHammer iteration is called the Athlon 64 3200+, which is aimed at desktops. It runs at 2 GHz and costs $417 each for a 1,000-unit batch. The differences between the notebook and desktop ClawHammers are not clear to anyone at this moment. I've looked at the spec sheets three times, and I can't see it, either.