The Four Hundred--IBM Raises the Curtain a Little on Future Power Chips, i5/OS V5R4

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Volume 14, Number 39 -- October 3, 2005

IBM Raises the Curtain a Little on Future Power Chips, i5/OS V5R4

by Timothy Prickett Morgan

While iSeries customers had been told to not expect any changes to the Power5 hardware and only minimal changes to the i5/OS software that comprises the i5 systems, there is still an expectation that the pSeries would get its hands on the Power5+ processors sometime this year. The top IBMers in the company's Systems Group who recently briefed IT Jungle on Big Blue's plans confirmed that the iSeries would not get Power5+, but would not say anything about the pSeries. These same IBMers provided some insight into the future Power6 platform and confirmed the rumors we have been reporting about features in next year's i5/OS V5R4 release, and divulged a few more details, too.

After the iSeries Town Hall meeting at the COMMON user group meeting in Orlando, Fla., two weeks ago, Alex Woodie and I sat down with Vijay Lund, vice president of server and storage development at IBM's Systems and Technology Group, and Jim Herring, director of product management and business operations for the iSeries Division. They provided a candid preview about forthcoming features in future products--without spilling the beans about the nitty-gritty details of the future iSeries and pSeries platforms. Like other server makers, IBM is inclined to give just enough details to whet the appetite and keep the stories rolling about its server platforms. Both IBMers were also eager to clear up a few rumors that have been running around, but did nothing to clear up the rumor about the presumably impending Power5+ announcement on the pSeries.

Back in August, I reported that the Power5+ crank on the Power5 processor was coming out in either September or October and that the Power6 chip had made first silicon (which it did, and I held it in my hands at COMMON). In our meeting with IBM at COMMON, Lund said that the Power5+ chip would not be delivered this year in the iSeries; he did not say anything about the pSeries. "We're doing great in the development laboratories with Power 5+," he explained. "It's just a matter of when we bring hardware, software, price, performance, yield, and cost all together."

(You can read the transcript of our conversation with Vijay Lund and Jim Herring, at COMMON briefing by clicking here. The latest information I have on the technical specs of the Power5+ chip is in this story, and I don't feel like repeating it all here.)

I will report whatever IBM says on October 4 about Power5+ in the next issue of The Four Hundred. All Lund would say further about the Power5+ chip is that it would have a "little bit of a frequency boost" and that because the thermal envelope of the chip will come down compared to Power5, there is the possibility that Power5 chips might end up on blade servers. "We're having those debates in the laboratory," he said. "We're not ready to say anything definitive right now, but it's a possibility."

The Power5 and Power6 chip projects were both started at the same time, right after Power4 came to market in late 2001, but the Power6 project is a much longer effort, Lund explained. He reiterated that the Power6 chip would be manufactured in a 65 nanometer chip making process, the most advanced technology that IBM has created to date for making chips, and revealed that the Power6 chip would have about 750 million transistors--nearly three times as many as the Power5. The single-chip version of the Power6 chip that Lund took out of his pocket was about 1.5 inches square and about a quarter inch thick, and the entire bottom of the chip was covered with gold knobs that Lund referred to as IBM's "C4" chip interconnect, a technology that he says is derived from Big Blue's mainframe technology. But the look of it, I would guess that Power6 has a very different interconnection scheme than the Power4 and Power5 chips had. But it is hard to say for sure.

Lund said that Power6 was due in 2007, and hinted that many system functions are going to be incorporated into the Power6 chip--things that might have otherwise ended up in custom ASICs on the systems or inside low-level microcode. And he said that Power7, which is probably due in the 2010 timeframe, is on the whiteboards now in IBM's chip design centers in Austin, Texas; Rochester, Minn.; and Poughkeepsie, N.Y.

Herring confirmed that with the Power6 servers, IBM would be moving to InfiniBand interconnections for servers (and IBM's pSeries brethren will be using InfiniBand as the interconnection for supercomputer clusters, too, at this time, replacing the "Federation" and "Colony" high-speed switches now used in IBM's RISC/Unix parallel supercomputers). But as far as the basic architecture of the Power servers--the Power4 "Regatta" and Power5 "Squadron" machines--Lund indicated that whatever was going into Power6 would not require a radical re-architecting of the servers.

Herring also confirmed that IBM was indeed working on a more direct link between outboard xSeries servers and the iSeries chassis and its internal disks, as we previously reported. But it is based on iSCSI, not just simple SCSI, and had I thought about it for more than 10 seconds I would have seen that. (Nobody is perfect.) SCSI has a limit of a few meters in distance between two devices, while iSCSI uses Ethernet fabric for the transport, which can have repeaters and thus put a pretty long physical distance between two logically close devices. (Duh.) With the rollout of the iSCSI link to the outboard xSeries boxes and BladeCenter blade servers, IBM also plans to do away with the Integrated xSeries Adapter co-processor, which hides under the skins of the iSeries chassis and comes in uniprocessor configurations only.

Herring also said that IBM would be delivering new RAID disk controllers that were more powerful and which supported the so-called RAID 6 extension to RAID 5, which provides an active hot spare in a RAID 5 array. IBM will also deliver a rack-mounted disk drawer that can hold 24 drives, but will not be moving to small form factor Serial-Attached SCSI (SAS) disks any time soon. SAS drives are on the iSeries roadmap, said Herring, but not in 2006.

Without being too precise, Herring said that i5/OS V5R4 would be delivered during the first half of 2006 and that it would have the functions I reported in the September 6 edition of this newsletter, including the elimination of the Input/Output Processors (IOPs) and a direct link between iSeries main memory and I/O Adapters (IOAs) that link peripherals to the iSeries. Basically, this used to be a three-stage asymmetric configuration, and now it is a two-stage configuration. The amount of I/O that gets put back on the iSeries is minimal--something that was not clear until now. This cuts some cost out of the i5 without impacting performance.

i5/OS V5R4 will also have a virtual tape server, as we previously reported, that will provide a way to back up OS/400 libraries to the Integrated File System on disk drives instead of using an actual tape drive to archive the data. This means that you can restore from those archived files (and presumably search through them) at disk-to-disk speeds. The IPv6 networking protocol will also be supported in i5/OS V5R4, and the operating system will have native spool file save and restore features for the first time.

Herring added two other things that I had not heard about a month ago. The first is that IBM is working to make SQL programming a little bit easier from inside RPG, and will also add a graphical SQL performance monitor to help iSeries shops understand the performance implications of their SQL queries and code--this sounds like a great feature.

And, finally, Herring said that IBM will eventually do away with the special Java Virtual Machine that the iSeries team long since created for OS/400 and embedded down into its guts back in 1998 with OS/400 V4R2. While this JVM offered very high performance on large AS/400 and iSeries boxes, Herring said that it did not scale down to smaller systems very well, and that customers needed to have a machine with 2,000 to 3,000 CPWs of performance and 1 GB of main memory to get decent performance out of it. This is obviously not acceptable. To that end, i5/OS will get the standard IBM JVM, which has a much smaller memory and CPU footprint, which just so happens to be the one used on IBM's Linux and AIX platforms. The integrated OS/400 JVM will be the default for i5/OS V5R4, with the standard IBM JVM being an option, but after that, the standard IBM JVM will eventually be the default in i5/OS as the older integrated JVM is phased out over time.