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Volume 1, Number 1 -- January 24, 2004

Intel Previews Xeon, Itanium Roadmaps

by Timothy Prickett Morgan

Intel's semi-annual shindig with programmers and system makers, Developer Forum, is only a few weeks away, but the company has started talking about its roadmaps for 32-bit Xeon and 64-bit Itanium server processors. The people heading up Intel's Enterprise Platforms Group have briefed reporters and analysts, but have not yet divulged all the details that will undoubtedly be spilled at IDF in February.

Much of the information that Intel gave out this week is a more precise version of information that the company divulged at the fall Developer Forum September. With Intel making only a few server-related processor announcement a year, it tends to go over the same ground a few times, raising the curtain a little higher each time until announcement day. This is ever the way in the IT racket.

In any event, Intel's briefings are, as usual, a cheerleading session for the 64-bit Itanium. Tom Garrison, who is marketing director for the Enterprise Platforms Group in Europe, said that Intel is working on six future generations of Itanium processors, which includes the dual-core "Montecito" due in 2005 and the multiple core "Tukwila" due after that in 2006 or so. Tukwila is being co-designed with the engineers who used to work on the Alpha processor at Digital and Compaq before Compaq dumped the line and sold the chip and its people to Intel. It was briefly known by the code-name of "Tanglewood," just so you don't get confused. The "Shavano" or "Chivano" dual-core Itanium that was originally due in 2006 was killed off in favor of making Montecito a dual core chip. What the code names are for the other four future Itanium chips, no one yet knows. (Shavano Park and Lake Tanglewood are both towns Texas, and may be where the code names come from. Who knows?)

Going forward, Intel plans to roll out a "Madison" Itanium 2 processor running at more than 1.5 GHz clock speed and having 9 MB of L3 cache memory. The current top-end Madison runs at 1.5 GHz and has 6 MB of L3 cache, and it seems likely that a 1.8 GHz or maybe even a 2 GHz Madison could be delivered as Intel ramps up its 130 nanometer processes.

In 2004, the dual core Montecito will come out with two cores and an incredible 24 MB of L3 cache memory, which will be made possible thanks to a shift from 130 nanometer to 90 nanometer processes by Intel. No one knows the clock speeds of Montecito, but it will probably be as fast as the fastest Madisons on the market at the time. By doubling up on cores, Intel can increase the performance of a "chip" by 80 percent or more and doesn't need to push clock speeds. In fact, Montecito could end up having a lower clock speed than the Madison chips. Montecito will be pin compatible with Madison.

Tukwila, which will probably have four cores but could include more, is apparently going to be done in the same 90 nanometer process, and Intel has said in past briefings that this chip would have at least ten times the power of the 1 GHz "McKinley" generation of Itanium chips and seven times the power of the 1.5 GHz Madisons. Four Itanium cores running at 2.5 GHz to 3 GHz will do the trick, but Intel could opt for six cores running at 1.5 GHz or eight cores running at 1.2 GHz. You see, the Itanium core is a lot smaller than the Xeon core, and Garrison says that for a given chip size, Intel can pack twice as many Itanium cores as Xeon cores on a die. The odds favor only four cores for Tukwila, of course, since it is hard to imagine Intel rolling out a four-core Xeon MP or Xeon DP processor. If you throw in HyperThreading simultaneous multithreading, you can shave the clock speeds by 25 to 30 percent to get the same performance.

McKinley, Madison, Montecito, and Tukwila are all now known as Itanium MPs. Intel will continue to deliver the HPC variants of the Itanium 2 chips for two-way servers, which have relatively high clock speeds, small caches, and low price tags compared to standard Itanium 2s. These HPC variants are known as Itanium DPs now. The 1GHz "Deerfield" variant of the Madison chip is also called an LV Itanium DP, for low-voltage. A kicker to Deerfield is expected in 2004 running at greater than 1GHz, and Intel is committed to delivering LV Itanium DPs out into 2005 and beyond.

On the blade server front, Intel will soon be shipping a variant of the four-way Xeon MP blade that it co-developed with IBM (and which Blue will be selling as the HS40 blade in a few weeks). Shipments for this blade server, which is code-named "McCarran," are slated for Q1 2004. The company also expects to ship its on Gigabit Ethernet host bus adapters and switches for its blade servers, which it sells to OEM customers, during the first quarter. Intel has also committed to bringing out an Itanium-based blade by 2005, probably using the low-voltage variants of the then-current chips.

As previously reported, Intel is getting ready to launch an improved "Gallatin" Xeon MP processor with 4 MB of L3 cache memory, which will plug into existing 32-bit Xeon MP machines and which will probably run at 2 GHz to 3 GHz, thanks to a move to 90 nanometer processes. That's pretty much it for 2004 for high-end 32-bit servers. In 2005, Intel will roll out the next generation "Potomac" Xeon MP processors. These chips were originally (and only vaguely) expected in the second half of 2004 along with the "Twin Castle" chipsets. In mid-2005, Intel will roll out a dual-core version of Potomac called "Tulsa," which will also plug into the Twin Castle chipsets.

In the two-way server space, Intel is expected to boost the cache size on the current "Prestonia" Xeon DPs to above 1 MB on existing 533 MHz frontside bus versions. Intel confirmed that the future "Nocona" Xeon DP chip, due in Q2 2004, will run at 3.2 GHz, have 1 MB of L3 cache, and will sport an 800 MHz frontside bus. Nocona it will be implemented in a 90 nanometer process as well. The Jayhawk Xeon DP, due in late 2004 or early 2005, will be essentially the same chip, but with a higher clock speed and possibly a larger L3 cache.

Both chips will make use of Intel's "Lindenhurst" and "Tumwater" chipsets for dual-processor servers, which are due in Q2 2004. Twin Castle, Lindenhurst, and Tumwater will incorporate support for PCI Express point-to-point I/O interconnections and will also support DDR2 memory subsystems. Motherboards using these chipsets will also support two Gigabit Ethernet links on board. All of the new Xeon MP and Xeon DP processors are also expected to include the "Prescott New Instructions" (also sometimes called SSE3) that were added to the Pentium 4 core for the latest 3.2 GHz chip (which is known as "Prescott" and which is not yet shipping). These instructions improve the performance of HyperThreading, among other things. We'll hear more about Prescott and SSE3 at IDF in a few weeks, to be sure.

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Editor: Timothy Prickett Morgan
Managing Editor: Shannon Pastore
Contributing Editors: Dan Burger, Joe Hertvik, Kevin Vandever,
Shannon O'Donnell, Victor Rozek, Hesh Wiener, Alex Woodie
Publisher and Advertising Director: Jenny Thomas
Advertising Sales Representative: Kim Reed
Contact the Editors: To contact anyone on the IT Jungle Team
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