Rock and Tukwila Were the Stars of ISSCC Last Week

Published: February 12, 2008

by Timothy Prickett Morgan

The two popular chip conferences held each year--the IEEE's International Solid State Circuits Conference in the winter and Stanford University's Hot Chips Conference in the summer--are like debutante balls for advanced microprocessors. This is where chip makers who have been shaping advanced technologies and bringing them to maturity announce them to the world. Last week, it was the ISSCC show, and Sun Microsystems, Intel, and IBM were talking about their latest processor designs.

The big star of the ISSC show last week was Sun's "Rock" UltraSparc RK multicore processor, and the presentation put together by Sun shows that it is indeed a 16-core, 32-thread processor. Sun's techies will be showing off a 2.3 GHz version of the chip that has 32 instruction threads from deep out-of-order retirement and sporting a new kind of main memory called transactional memory. The Rock chip also has an additional 32 scout threads--one per instruction stream--that preprocess information before it is dumped into the instruction stream in an effort to boost the efficiency of the chip. The chip that Sun was showing off last week was implemented as a 65 nanometer and has an area of 396 square millimeters. Sun is boasting that the Rock chip will have high performance on both single-threaded and multithreaded applications, which is a neat trick. The move to 65 nanometer processes should allow Sun to eventually get the clock speeds of the Rock chips into the 3 GHz range, but maybe Sun is having issues with this, much as Advanced Micro Devices is having with its quad-core "Barcelona" Opterons, which are going to be about nine months late coming to market when they finally do in volume and without the cache bug that was discovered in them last fall.

Sun is also expected to show off the floating point processing capabilities of the Rock chip, as well as the sophisticated memory arrays, register files, and mainframe-class reliability enhancements in the processor. It is unclear if Sun will confirm the rumors about whether or not the "Supernova" servers using the Rock processors have been pushed out from their promised delivery date of the second half of 2008 by a year. I am working to get someone at Sun to talk to me about this right now. I will also give you the lowdown on transactional memory and what it can do for the future Sparc systems.

Intel was showing off its future "Tukwila" quad-core Itanium processor, which is expected later this year. According to Intel's presentation, the Tukwila chip will weigh in at over 2 billion transistors and will be implemented in the 65 nanometer, eight-layer process that Intel is in the process of retiring on its Xeon and Core processors as its ramps up its 45 nanometer processes. The Tukwila chips have three times the transistors of the current "Montvale" dual-core Itanium 9000s and are 700 square millimeters in size. Each of the four cores on the Tukwila chip has HyperThreading, giving each chip eight instruction threads, and 30 MB of L3 cache memory on the chip, up from 24 MB on the Montvale and "Montecito" dual-core Itanium 9000 chips. Intel is also showing off its HyperTransport-alike interconnect for processors, memory, and I/O called QuickPath, which Intel says will enable processor-to-processor bandwidth of 96 GB/sec and peak memory bandwidth of 34 GB/sec. The Tukwila chips are expected to range from 1.2 GHz to 2 GHz in speed and offer about twice the performance of the current 1.66 GHz Montvales. The chips are apparently quite hot--apparently as high as 170 watts--which begs the question as to why Intel is not implementing Tukwila in 45 nanometer technology to shrink it and let it run cooler at the same clock speeds or even higher. Shrinking a big chip is not easy, however, and manufacturing processes are tied pretty tightly to a chip design so changing one affects the other. That means you can't just throw the Tukwila design on the board and shrink it to 45 nanometers in a day.

Intel's techies are also expected to outline voltage-frequency scaling techniques that allow the Tukwila chip to operate at lower voltages and therefore consume less power.

IBM was expected to detail the work its Microelectronics division is doing as it transitions its "Cell" Broadband Engine variant of the Power architecture from a 65 nanometer silicon-on-insulator (SOI) process to a 45 nanometer SOI process. The Cell chips, which run a bit hot because they are so large but which have lots of adjunct processors that allow them to provide stellar computational and graphics performance, could use such a shrink to be more useful and maybe to boost performance. IBM says that the shrink on the Cell chips cuts the chip area by 34 percent and power consumption by 40 percent, presumably at the same clock speed.

Tilera, the startup chip maker that launched a 64-core processor last summer at the Hot Chips event, was talking up the Tile64 chip at ISSCC last week. The Tile64 processor is not based on an existing instruction set, such as X86 or MIPS, but rather on a whole new instruction set that is geared for low power and designed to run a homegrown variant of Linux tuned for the architecture. Hitachi and Waseda University in Japan were showing off an eight-core 600 MHz system-on-a-chip design they put together and created a parallelizing compiler for that can deliver 33.6 gigaflops of number-crunching performance. It is not clear if this chip is based on Hitachi's Super-H RISC instruction set, but it probably is.

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