IBM Tweaks Cell Chip, Moves to 65 Nanometer Process

Published: March 20, 2007

by Timothy Prickett Morgan

Chip maker IBM said last week that it has tweaked its Cell Broadband Engine variant of the PowerPC chip and moved its production to a 65 nanometer chip making process.

The Cell chip, of course, is a variant of the PowerPC architecture that was co-developed by IBM, Sony, and Toshiba. Sony is the volume user of the Cell chip, putting it inside its PlayStation 3 game console, while IBM and a few partners are dabbling in making blade servers based on the Cell chip for doing real-time, high-resolution rendering for medical and military applications. Toshiba will eventually use Cell chips in an array of electronics.

The original Cell chip, which was formerly launched in September 2005 but which only began appearing it products a year later, had a single 64-bit PowerPC core (derived from the PowerPC 970 core, including the AltiVec vector co-processor); it also has eight special co-processors, which IBM calls synergistic processor units, which can be programmed to do interesting things, like render very complex images with near-real time speed. The chip also has 64 KB of L1 cache and 512 KB of L2 cache memory and an integrated Rambus XDR main memory controller. These Cell chips were based on a 90 nanometer process ran at 3.2 GHz.

Considering the size of the chip and its clock speed, IBM could not cram more than two of them on a blade server. IBM's QS20 blade server has only 512 MB of XDR main memory and a single 40 GB disk. The blade delivers 410 gigaflops of computing power, which is a lot. The blade has two InfiniBand ports and two Gigabit Ethernet ports for linking to other machines and storage in supercomputer clusters. These blades are part of the 1.6 petaflops hybrid supercomputer that Big Blue is building for Los Alamos National Laboratory, dubbed "Roadrunner." About 80 teraflops of that Roadrunner machine is based on an Opteron cluster running Red Hat Linux; the rest is all Cell.

By moving to the 65 nanometer silicon-on-insulator (SOI) process that the company is also using in its East Fishkill, New York, labs to make its Power5+ and Power6 processors, IBM can crank up the clock on the Cell chip, giving it a substantial boost in performance. According to technical papers IBM researchers delivered recently at the IEEE's International Solid State Circuits Conference, the revamped Cell chip can crank up to 6 GHz with the new chip making process and running at 1.3 volts. The interesting innovation with this Cell revamp is that IBM is apply different voltages to the core and SRAM used in L1 and L2 caches, rather than the same voltage for both, which increases the stability of the SRAM while also allowing for power consumption for the Cell chip to be reduced.

IBM did not say when the new chip would be put into production by Sony or when it would be available in its own QS20 blade servers.

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