Sun Releases OpenSparc T1 Specs, As Promised

Published: March 28, 2006

by Timothy Prickett Morgan

Sun Microsystems last week used the Multi-Core Expo in Santa Clara, California, as the coming-out party for the open sourcing of the specifications for its OpenSparc project, which is an open and royalty-free implementation of the "Niagara" Sparc T1 processor that Sun announced earlier this year.

In the past year, Sun has open sourced or announced plans to open source its Solaris operating system, its Java Enterprise System middleware stack, and the T1 processor. Last week, Sun made available the hardware designs--specifically, the Verilog Register Transfer Level, or RTL, specs for the OpenSparc T1 chip--which allow chip engineers to study and to tweak the T1 chip design. Sun is also making available the verification suite and simulation models for the chips and Solaris 10 Unix simulation images. These features are being released under the GNU General Public License v2.

In mid-February, Sun had taken the first steps toward open sourcing the T1 chip when it released a freebie UltraSparc Architecture 2005 specification and the companion HyperVisor API specification for the T1 chips. The T1 chip is the very first Sun chip to use a microcode-based hypervisor layer, which will allow it to virtualize chip features and to support multiple and incompatible operating systems on the processor. Some of the virtualization is done in hardware, some is done in microcode. These two specs are the basic documentation that techies need to understand to port other operating systems to the T1 chip, which is why Sun announced them first. Community members immediately set about porting Linux and BSD Unix to the T1s, and Sun clearly hopes other operating systems will follow. Sun is showing off an early Linux port at the Multi-Core Expo, in fact.

Sun is also getting some serious backing for the OpenSparc project. The University of California at Santa Cruz is contributing source code for performance simulators for the chip, which the university can do because it had beta access to the T1 designs. These performance simulators allow chip designers to change caches, clock speeds, and other features in the chip design and then predict how the chip will perform--all within a simulated environment. Another company called Aldec, which provides Verilog design verification tools, is offering a free 90-day download of its Riviera Verilog Simulator to OpenSparc members.

Sun also got an endorsement from David Patterson, an uber-nerd from the University of California at Berkeley who helped create the RISC chip architecture and RAID disk arrays, who is president of the Association for Computing Machinery, and who is working on an FPGA-based supercomputer project called RAMP along with colleagues at the Massachusetts Institute of Technology, Stanford University, Carnegie Mellon University, the University of Washington, and the University of Texas, says that the T1 design is interesting and that he is looking at expressing the T1 chip in the RAMP machine's FPGAs. Sun says that it is working with the RAMP project to port the T1 architecture to RAMP and build a 1,000-core research system.

Fabrizio Fazzino, a professor of computer architecture and a member of the faculty of engineering at the University of Catania in Italy has started a company called Simply RISC, which will be creating a single-core implementation of the T1 processor for the embedded market.

The T1 processor is interesting in that it has eight Sparc cores, each with four threads, on a single die, and it consumed between 72 watts and 79 watts of electricity when it is running. This chip can do the work of two Intel Xeon processors on infrastructure-type workloads, which take several hundreds of watts to do their work. This chip is available in Sun's own T2000 servers, which were launched earlier this year.