Volume 4, Number 13 -- April 10, 2007

X4 Chipset from IBM Tuned for Tigerton Quad Core Xeon MPs

Published: April 10, 2007

by Timothy Prickett Morgan

Server maker IBM is prepping its fourth generation of chipsets for creating scalable SMP servers out of Intel's Xeon MP processors. The X4 chipset, which according to Jay Bretzmann, marketing manager for high-end System x servers at Big Blue, does not have a code name, has features that make it suitable for multicore processors with very large memories.

The X4 chipset is the kicker to the current "Hurricane" X3 chipset, which supports the single-core Xeon MP and dual-core "Paxville" Xeon 7000 and "Tulsa" Xeon 7100 processors from Intel. None of the Xeon MP chips use the energy-efficient Core architecture, as Intel's other 64-bit chips for laptops, desktops, and entry servers do. But the future "Tigerton" and "Dunnington" Xeon MP chips will be based on these updated X64 cores. The details about Tigerton are a little thin, but it looks like it is based on the current dual-core "Woodcrest" chip, and like the "Clovertown" Xeon 5300, will cram two dual-core chips into a single CPU socket. Tigerton is slated for sometime in the second half of this year, and IBM is ready to go with the X4 chipset when Intel has Tigerton out.

The difference, however, is that Tigerton will have a new bus structure, which Intel detailed back in October 2005, called the Dedicated High Speed Interconnect. With the current set of Xeon MP chipsets, all four CPU sockets on a system board share a single front side bus. The Dedicated High Speed Interconnect connects the CPU sockets directly to the chipset on the motherboard, but main memory talks to the chipset, not directly to the CPU cores. Tigerton is based on Intel's current 65 nanometer chip process technologies, while Dunnington could be a 45 nanometer shrink of the Tigerton part, but it is probably based on the "Penryn" cores that are due later this year and early next in the Xeon DP lineup.

Tigerton replaces a failed chip called "Whitefield," which was supposed to be a quasi quad-core variant of Woodcrest that used the Common System Interconnect (CSI) for Xeon and Itanium chips that Intel pushed out to its "Nehalem" cores due in 2008. (See Intel Shows Off Future Penryn and Nehalem Chip Designs for more on the future Intel chips.)

According to Bretzmann, aside from support for the new bus architecture that is coming with Tigerton and Dunnington, the X4 chipset will support considerably more main memory. With the X3 chipset that is shipping now in the System x server line, each system board has 16 main memory slots and can support 1 GB, 2 GB, and now 4 GB DIMMs. The X3 chipset scales up to eight system boards, for a total of 32 CPU sockets in a single system image used SMP-like NUMA clustering. With the X4 chipset, IBM will extend support to 32 processor sockets again, but will double the number of main memory slots to 32 per system board and up to eight systems boards in a single image, for a total of 256 memory slots. Considering that 2 GB DIMMs are now affordable, 4 GB DIMMs are coming down in price, and 8 GB DIMMs are right around the corner (probably by year's end), the top-end X4 server could support up to 1 TB of main memory out of the box with 4 GB DIMMs and be available with 2 TB of main memory soon thereafter. This is as much main memory as any RISC/Unix architecture can bring to bear.

"With the X3 servers, we have discovered the increasing importance of memory," says Bretzmann. "Virtualization is often bottlenecked by memory, so bringing more memory to bear is important. This is one reason we are seeing a renaissance in scale-up architectures."

More main memory as well as large L2 and L3 cache memories are also important in systems that have multicore processor designs. By moving from two to four cores per processor socket--that's a maximum of 128 cores per X4 system--applications using those cores need to have sufficient memory to keep them fed with data in an efficient manner. In many cases, because of power and cooling issues, a blade server or a 1U rack server will not have sufficient memory to balance against the jump from two to four cores. Customers buying IBM's big Xeon SMP boxes will not tolerate such a bottleneck.

The future X4 servers can be hard partitioned by simply unplugging system boards from each other, and will obviously support a variant of hypervisor-based partitioning. VMware ESX Server and XenSource XenEnterprise are the obvious hypervisors to choose from, but ESX Server 3 can only span four processor cores in a single system image and Xen Enterprise 3.2 can only span eight cores. Customers buying big X4 boxes would probably like a hypervisor that can span all the cores in the box, if they so choose.

The X4 chipset will probably not have native InfiniBand ports on the motherboards, since the high-end System x servers are generally not used for supercomputing clusters. The X4 boards are also expected to have dual native Gigabit Ethernet ports, with 10 Gigabit Ethernet ports as a peripheral option, just as with the current X3 chipset.


Intel Shows Off Future Penryn and Nehalem Chip Designs

IBM Launches Promised 32-Way Intel Server

Intel Pushes Out Itaniums, Replaces Future Xeon MPs

IBM Plans X3 "Hurricane" Chipset for Xeon Servers

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Editor: Timothy Prickett Morgan
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