Intel Establishes Cross-Divisional HPC Unit

Published: May 8, 2007

by Timothy Prickett Morgan

Chip maker Intel has set up a cross-divisional business unit devoted to high performance computing, and has appointed Richard Dracott as general manager of the unit.

Dracott was previously director of marketing for Intel's Enterprise Platforms group, which was merged two years ago with the desktop chip business to create the Digital Enterprise group. The plan for the unit is to tap into the substantial growth in the HPC server space, which accounts for more than $10 billion a year in sales (about a fifth of the market) and which is growing at a substantially faster rate than the overall server market itself (about 10 percent compounded annually, reaching about $14 billion by 2010). William Camp, the director of Sandia National Laboratories where Intel's ASCI Red massively parallel supercomputer was deployed more than a decade ago, has been tapped to be the chief technology officer of the HPC group at Intel as well. The HPC unit will have input over include semiconductor process, chip design, and software technologies created by Intel.

Having been at the top of the supercomputing heap for many years, a resurgent Intel with a much-improved chip architecture and the right kind of cool-running processors is now going to chase the HPC space at the high end with capability-class machines, in the middle with modest clusters, and at the low-end with so-called personal supercomputers.

"We see HPC as an area where we can take new technology to market, and then bring that technology to a broader market later," says Dracott. "And we are going to go after the really large deals, in the Top 50 rankings, too." He says that Intel expects that Core and Itanium processors will be in the Top 50 supercomputer rankings, which is the upper one-tenth of the semi-annual Top 500 rankings put out by the University of Manheim and the University of Tennessee.

One such new technology that is focused on HPC is the 80-core experimental processor, code-named "Polaris" and now known as the TeraFlops chip. A few weeks ago, at Intel Developer Forum in Beijing, China, Intel was showing off a version of this streamlined RISC chip that delivered 2 teraflops of aggregate number-crunching power--twice the performance of the 3.1 GHz chip that Intel talked about in the summer of 2006. The TeraFlops chip puts the cores (which are probably floating point units derived from the i860 and i960 RISC processors Intel developed more than a decade ago) in an 8x10 array on the chip. A router to link the cores to each other and to memory is embedded in the silicon; a 20 MB SRAM that is stacked on top of the chip and bonded to it, which yields thousands of links between the cores and memory, rather than the hundreds that link a CPU to an outside memory bus in conventional X64 designs. This chip and memory stacking technique can terabytes per second of memory bandwidth, which matches up against the teraflops of computing power.

Intel has said that it expects to deliver a commercial product based on TeraFlops within about five years. Given that Intel has decided that attaching co-processors for accelerating servers belong on the PCI-Express bus, you might think that a spin-off for the TeraFlops chip will end up on a co-processor card. But long-term, starting with the "Nehalem" generation of Core processors coming in late 2008, Intel will bring its Common Systems Interconnect to market, and it is more likely that Intel will conclude, as many Opteron enthusiasts have, that a processor socket linked by HyperTransport is the way to drop co-processors into systems. Whatever the CSI analogs will be to the Opteron socket and HyperTransport, this is probably what Intel will actually use to deploy co-processors like TeraFlops.

"We believe that the long-term solution for computing is to take advantage of multiple cores," explains Dracott. "We are looking at how we propagate clocks across so many cores, how we group the cores, how we turn them off and on as they are used. There is a lot of device management and device physics involved in such a product."

RELATED STORIES

Intel Details Future 45 Nanometer Chip Plans from Beijing

Intel Previews Quad-Core Chips, Talks Up Massively Cored RISC

                     Post this story to del.icio.us
               Post this story to Digg
    Post this story to Slashdot