AMD Revises Opteron Roadmaps, Pushes Out Rev Gs
Published: May 13, 2008
by Timothy Prickett Morgan
Hoping to build some confidence in its processor roadmaps, Advanced Micro Devices last week was talking more specifically about its Opteron and Athlon X64 processor plans between now and 2010. With the difficulties of the "Barcelona" quad-core Rev F Opterons for two-socket and larger machines behind it and the "Budapest" quad-core variants for single-socket boxes coming this quarter, AMD has taken a hard look at its roadmaps and made some important changes--changes that should improve its chances of keeping pace with a resurgent Intel.
What is immediately obvious after reviewing the new AMD processor roadmaps is that the eight-core "Sandtiger" Opteron processor, which was going to plug into the new Rev G socket, now known as the Socket G34, has been thrown onto the scrap heap. AMD first started talking about the Sandtiger kicker to the now-current Socket F1 Barcelona and Budapest chips last August, when it became clear that Barcelona was going to be delayed. Not only is the Sandtiger family of eight-core chips gone, but the Rev G socket that it was designed to plug into has been pushed out to 2010 from its original 2009 launch date (according to the roadmaps from last summer, anyway). It now becomes apparent why the heads in marketing and engineering have been rolling lately at AMD.
Many of the Sandtiger features are being put into the revised Opteron and Althon products, of course, and the transformation of the Sandtiger products into the new X64 chips is really AMD's desire to better hit the sweet spots in the server and workstation market in terms of core counts and clock frequencies than the eight-core Sandtiger family would have done. The lower core count will allow not only higher chip yields potentially--if AMD even decides to keep fabbing its own chips--but will also allow the clock cycles to be boosted. This is why Intel's future Xeon chips are moving to six cores per die, and AMD has little choice but to follow. And the same holds true--and many observers of the chip industry have noted--with AMD having to concede that multichip packaging, such as that pioneered by Hewlett-Packard for the Itaniums and then by Intel and IBM for their Xeon and Power processors to boost the performance per socket in their chips, is not always a bad idea if the chip is architected for it. (And, to Intel's credit and profit, maybe even if it isn't.)
Randy Allen, general manager of AMD's server and workstation division, didn't even mention the Sandtiger processor in his briefing with the IT press last week as he laid out the new chip roadmap, and AMD is not even issuing a press release about the roadmap even if it is putting the information out on its Web site. Allen said that the "Shanghai" kicker to Barcelona is on track for shipments at the end of this year as AMD transitions from the 65 nanometer processes used to manufacture the Barcelona and Budapest Opterons to a 45 nanometer immersion lithography technique that is going to allow AMD to boost its quad-core processor performance by about 20 percent compared to the current quad-cores. The Shanghai chips will have 6 MB of shared L3 cache (more than three times that of the Barcelonas) and 512 MB of L2 cache per core (double that of the Barcelonas). The AMD-V hardware assisted virtualization features are also being improved to allow for 25 percent faster virtual machine migrations inside a system. The Shanghai chips will support 800 MHz DDR2 main memory as well, which runs about 10 percent faster than the 667 MHz DDR2 main memory used with the Barcelonas. The Shanghai chips will also include support for the HT-3 HyperTransport interconnect, and will plug into the existing Socket F1 CPU sockets (formerly known as the Rev F socket or the Socket 1027). nVidia nForce 3050 and 3600 chipsets and Broadcom HT-1000 and HT-2100 chipsets will therefore support the Shanghai chips, just as they supported the dual-core "Santa Rosa" and quad-core Barcelona Rev F chips.
The Shanghai processors will be available in standard, Special Edition (SE for short, and meaning higher clock speed and much hotter temperature), and Highly Efficient (HE, and meaning lower voltage and therefore lower heat for a given clock speed) variants. Allen said that the Shanghai chips are sampling now to server and workstation partners, who are now doing their platform validation on the chips; he did not elaborate on what clock speeds the chips will run at.
With Sandtiger gone, AMD has to do something in 2009, and it is therefore going to extend the life of the Socket F1 and crank out a new monolithic, six-core chip code-named "Instanbul," which is expected to come to market in the second half of 2009. The addition of two more cores to the basic Shanghai design will be accompanied by a number of small tweaks, and while the extra cores could, in theory, deliver as much as a 50 percent boost in performance for heavily threaded applications, Allen is cautioning that customers should expect a something more in the range of 20 percent or so more oomph in the jump from Shanghai to Istanbul chips. (Incidentally, AMD's latest generation of X64 chips are all based on the cities where Formula One races are held.)
In the single-socket server and workstation space, 2009 is all about a kicker to Budapest called "Suzuka," which is a quad-core variant of the Shanghai core that will also be implemented in 45 nanometer technologies and that will very likely have higher clock speeds and will pull in support for DDR3 main memory. The Suzuka chip is expected in the second quarter of 2009, and will make use of AMD's RS780 chipset and its companion SB700S southbridge for I/O. It is not clear if nVidia or Broadcom will do chipsets, but they are not on the roadmaps, so they should mean something. The Suzuka chip will plug into "Catalunya" platforms, which is very likely a cut-down version of the Socket G34 chip socket. In this sense, the Suzuka is a beta test for the future Rev G chips for larger servers. Suzuka chips will probably have higher clock speeds than their brethren at the higher end of the server and workstation line, given the lower core count and the absence of multithreading for a lot of entry server and workstation applications.
For two-socket and larger servers, the first half of 2010 will see the reimplementation of the six-core Istanbul design in a chip called "San Paolo" that will sport a 12 MB L3 cache (twice that of Instanbul), DDR3 main memory, four-lane HT-3 HyperTransport links and a bunch of other features that will deliver what Allen calls "a modest performance boost" over the Istanbul chips. That sounds like maybe another 20 percent bump, maybe more if AMD can get yields on the 45 nanometer processes it is using to make the San Paolo chips. And for customers who have workloads that like threads, AMD will also debut its first two-chip packaging for a single CPU socket with a variant called "Magny-Cours," that will put two of these San Paolo chips in a single socket, for a total of 12 cores in the same thermal and power envelope as today's Barcelona equivalents. These 12-core packages will have lower clock speeds per core to stay in the same thermal envelopes and therefore offer customers a way to choose the best Opterons for their workloads.
The San Paolo and Magny-Cours Opterons will make use of AMD's "Maranello" platform, which has the G34 socket and which is implemented currently using AMD's RD870S and RD890S chipsets and the SB700S southbridge for I/O. The chipsets will support PCI Express 2.0 peripherals and will also sport electronics for virtualizing I/O through a feature called the I/O Memory Management Unit. This feature is akin to Intel's VT for Directed I/O feature on its Xeon processors and often called VT-d. IOMMU will extend support of virtualization in the Opteron chips from the instruction set with the AMD-V instructions out to I/O functions. This feature was originally expected with the now-defunct Sandtiger chips in 2009.
Server Makers Start Shipping Barcelona Boxes
AMD to Slash 10 Percent of Workforce Amid Sales Shortfall
Intel Talks Up X64, Itanium Roadmaps Ahead of IDF
AMD Says Barcelona Bug Is Fixed, Almost Ready to Ramp
AMD Stalled by a Bug in Barcelona Opterons
Intel Announces First "Penryn" Xeon Processors
AMD Gets Aggressive About Watts with Quad-Core Barcelonas
Chief Marketeer at AMD Quits Before Barcelona Launch
AMD's Chip Roadmaps: Beyond Barcelona
Intel Cranks Out Two More Quads, AMD Sets Barcelona Date
AMD Gooses Dual-Core Opteron Speeds, Cuts Prices
Intel Sets Up 'Tigerton' Xeon MPs Against Future Opterons
AMD Sets 'Barcelona' Quad-Core Opteron Launch for August
Intel Delivers Low-Power, Quad-Core Xeon Chips
AMD: Native Quad Core Opteron Will Best Intel Quasi Quads
Intel Delivers More Quad-Core Server and PC Chips
AMD Unveils Rev F Opterons, Prepares for Quad Cores in Mid-2007