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Volume 2, Number 21 -- May 31, 2005

AMD Publishes Pacifica Virtualization Spec

by Timothy Prickett Morgan

At the end of March, chip maker Advanced Micro Devices said that it would be publishing the specification for the "Pacifica" instruction set virtualization technology that it will be embedding in its processors sometime during the first half of 2006. Last week, at the LinuxWorld Summit in New York, AMD did what it said and put the spec out there for all to see.

If you have trouble sleeping at night, or you think hardware and software engineering specifications read like mystery novels or thrillers, you can get your copy of the Pacifica spec at this link.

Not many people will read the specification, since it is not really aimed at the broader market of application software developers. According to Margaret Lewis, commercial software strategist at AMD, the Pacifica instruction set virtualization technology is really only something that operating system, hypervisor, and low-level systems management software makers need to worry about.

In terms of the X86 platform, that means Microsoft for Windows; the open source Linux community and the commercial Linux distributors such as Red Hat, Novell, Mandriva, and Turbolinux for Linux; and Sun Microsystems, SCO Group, and the three open source BSDs for their respective variants of Unix. (Novell may also be keen on using Pacifica to support NetWare, too.) The hypervisor and virtual machine software providers on the X86 and X64 platforms these days are VMware with its GSX and ESX Server, Microsoft with Virtual Server 2005, and the open source Xen project and its commercialized variant from XenSource. (Technically, Xen and ESX Server are hypervisors, which run on bare iron and provide isolated partitions, while the others are hosted virtualization products, which run a virtualization software layer on top of an operating system and run guest operating partitions on top of that virtualization later. If the host operating system dies, it takes down the whole machine. With a hypervisor, there is no host operating system to die.) Either way, these products allow an X86 or X64 server to be carved up into virtual slices, each equipped with their own operating system and software stack. Virtual Iron, a new virtualization vendor that gloms together servers into one virtual space (which can then be carved up into dynamic virtual pieces), will also be interested in the Pacifica spec. And any system management software provider that wants to manage the provisioning of X86 and X64 servers will have to have hooks into Pacifica technologies as well.

Everything I just said about Pacifica will apply equally to Intel's embedded instruction set virtualization electronics for its Xeon and Itanium processors, which is known as Virtualization Technology or VT. If Intel and AMD do their jobs right, none of us will need to worry about whether or not these features work; it will be utterly transparent to the applications.

While VT and Pacifica will perform essentially the same functions on their respective Xeon/Itanium and Athlon/Opteron processors, they are not, strictly speaking, compatible--and nor can they be. According to Lewis, the underlying differences in the chip architecture make this impossible. For instance, Opteron chips have HyperTransport links and an integrated memory controller, while Xeon chips have a front side bus and an external memory controller. These differences, which are masked by the virtualization software, have to be dealt with independently by that virtualization software. However, Lewis says that the code modifications will be minimal, and they will only affect the operating system, hypervisor, virtual machine partitioning, and systems management vendors that go down into the virtualization layer.

The big payoff, of course, is that instruction set virtualization will be embedded in systems (much as 64-bit processing is today in the X86 market), and that will allow companies and consumers to do more interesting things with their machines, such as run two operating systems at once, side by side. Aside from the transparent nature of the virtualization in future machines, the biggest benefit that Pacifica and VT will bring is performance. On many workloads, using software-based virtualization technologies can impose a performance penalty of anywhere from 10 to 40 percent, according to Lewis. AMD pushed the X86-64 instruction set, which first brought 64-bit memory addressing to the X86 chip architecture, and had a goal of doing so without impacting performance. As it turned out, some applications took as much as a 3 percent performance hit moving to 64-bit addressing, but the vast majority saw a gain in performance that was as large as 3 percent (that is without actually recompiling the applications, but rather running a 32-bit application on a 64-bit capable chip). Essentially, the performance hit associated with the X86-64 extended instruction set was nil except in special cases. AMD has the same goal with Pacifica. "Our goal is to enable virtualization software to run with little or no performance degradation," said Lewis. And that is equivalent to getting a 10 to 40 percent performance boost compared to current software-based virtualization technologies.


AMD Readies Pacifica Spec, Hires IBM System Expert

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Editor: Timothy Prickett Morgan
Contributing Editors: Dan Burger, Joe Hertvik, Kevin Vandever,
Shannon O'Donnell, Victor Rozek, Hesh Wiener, Alex Woodie
Publisher and Advertising Director: Jenny Thomas
Advertising Sales Representative: Kim Reed
Contact the Editors: To contact anyone on the IT Jungle Team
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