Intel Bangs the Itanium Drum, Draws Out Roadmap
Published: June 19, 2007
by Timothy Prickett Morgan
Chip maker Intel, which is in the midst of a substantial technological turnaround with its X64 chips for laptops, desktops, and servers, doesn't want the world to think that it has forgotten about Itanium, the step-child that it more or less adopted from Hewlett-Packard a decade ago to create a better and more elegant processing architecture that was--and you must remember this--supposed to replace the 32-bit X86 chip utterly and completely. That didn't happen, of course, but Itanium has found its place in the data centers of the world.
Diane Bryant, vice president and general manager of Intel's Server Platforms Group, hosted a conference call with the IT press to talk about the Itanium processor's traction in the market and, as Intel does from time to time, raise the curtain a little bit on the Itanium chip roadmap. From 1999 through 2004, that roadmap changed a lot, and if there is one thing that Intel wants more than anything, it is to prove two things: that Intel will deliver competitive performance increases with Itanium chips and that the roadmap goes out further than anyone need worry about.
The reason why Intel and its Itanium partners want to constantly remind us of this is that the X64 platform, which Intel basically controls, accounts for over 90 percent of server shipments worldwide, and given this market penetration, the long-term viability of any alternative server processor would seem to be called into question. But according to data from IDC, the $58 billion server market in 2006 was neatly split between X86/X64 platforms on one side and very pricey but very reliable and scalable RISC, Itanium, and mainframe platforms on the other side. The charts and roadmaps from the late 1990s may have shown Itanium eating everything, and all operating system vendors of the time were enthusiastic in their support of Itanium--including Unix vendors Sun Microsystems and IBM, which unplugged their Solaris and AIX platforms from Itanium. Maybe that will change, someday, but right now, all the vendors that sell Itanium products want to do is increase Itanium server sales from 2006's $3.4 billion level, which was up 40 percent year over year. And, they are on track to do it; Itanium platform sales have been growing faster than Sparc and Power platform sales for years. (Intel estimates that the total cumulative investment in Itanium-based server sales is around $8.7 billion since 2001.) All Intel knows for sure is that it wants a bigger slice of the RISC/mainframe half of the server biz.
The main reason why Itanium has seen growth is that the single-core "McKinley" chip from 2002 provided acceptable performance, and the kicker "Madison" Itanium 2 was competitive with everything excepting IBM's Power5 chips; the dual-core "Montecito" Itanium 9000s announced last summer give all chips, including IBM's Power5+ and Sun's UltraSparc-IV+, a serious run for the money. It doesn't hurt that HP-UX and OpenVMS customers do not really have any alternative but to invest in an Itanium-based system or move their applications to an entirely new operating system/server combination. This is what HP's Tru64 Unix and HP 3000 customers face, in fact. But to be fair, the systems built using the Montecito chips and supporting HP-UX, Windows, Linux, and OpenVMS deliver more performance at a lower cost than their predecessor RISC platforms (in the case of HP-UX and OpenVMS) and deliver scalability, reliability, and other high-end features that are commonly not in X86 and X64 Windows and Linux systems.
This is why there are now 12,000 applications on the Itanium architecture (across many operating systems and double the level from last year) and more than 140,000 Itanium-base servers have been shipped worldwide to date. And the very good performance of the Montecito chips launched last year--which were a year later to market than they should have been, if you want to be generous--is the main reason why Intel has sold twice as many Montecito chips (which means four times as many processor cores) in the second half of 2006 than it sold of single-core Madison chips in the last six months of 2005.
All of this is encouraging to companies investing in the creation of Itanium-based products and to the customers who invest in them and to a certain extent stake their businesses (and the careers of their IT staff) on them. And so is a nice, long roadmap.
And so, Intel last Thursday explained a little bit more about the future "Tukwila" Itanium processor, due to come to market at the end of 2008, as well as the "Poulson" kicker and the "Kittson" follow-on.
But before we get to Tukwila in 2008, we have "Montvale," a tweak of the current Montecito design, coming out in the second half of 2007. Montvale will sport faster front side buses than the current Montecito chips (which were supposed to have faster FSBs in several of the earlier roadmaps, but didn't get them). Montvale will have unspecified reliability features added to the mix as well.
The Tukwila Itanium chip will be implemented in Intel's 65 nanometer process, and last week the company confirmed that it will indeed be a quad-core, monolithic die. Bryant did not talk about L2 and L3 cache sizes on Tukwila, and she would say nothing about clock speeds, either. She did say that it would have Intel's HyperThreading simultaneous multithreading, would fit into the thermal envelope of the current Montecito dual-core chips, and would deliver twice the performance of the Montecito. This would seem to suggest that Intel is going to be able to get above the 1.6 GHz clock speed of the Montecito chips (clocks were once in the range of 2 GHz in early Montecito test machines).
Aside from having twice as many cores, Tukwila will also employ the Common System Interconnect (CSI) features that Intel was talking about for its future "Nehalem" update to the Xeon processors back in March. With the CSI approach, Intel is brining main memory and cache controllers onto the chip and making chip-to-chip interconnects like IBM's Power and Advanced Micro Devices' Opteron chips have. Nehalem is due in 2008 as well, but on a 45 nanometer process and with eight processor cores per die. (As usual, Itanium is lagging in the core count, but delivers about twice the performance per core.) Bryant also said that with Tukwila, Intel will launch a unified chipset that works for both Itanium and a future family of Xeon processors (which probably means Nehalem, but she didn't say). That also means Tukwila chips will not plug into Madison and Montecito sockets.
Tukwila will also have a memory scrubbing technology called Double Device Data Correction, which allows a memory DIMM in a server to keep running even after it has two sequential memory hard errors; Itanium systems today can cope with one such DIMM fry, but two in a row crashes the box. But not with DDDC.
Bryant did not say much about the future Poulson Itaniums. It will be implemented in 32 nanometer technology, Bryant said. And given that the kicker to Nehalem, called "Westmere," is due in 2009 using a 32 nanometer process and Intel likes to have a year or two to get high yields on a new process before using it on the large die sizes of Itanium chips, that probably means Poulson is coming in 2010 or 2011. Intel is not implementing Poulson in 45 nanometer technology because it wants to use the smaller (and further out) chip process as a means of putting more features in the Poulson and using the extra time in development to do a refresh on the Itanium microarchitecture, which hasn't really changed since 2002. Poulson is expected to have more cores, more threads, lots of caches, and lots of parallelism. Poulson chips will plug into Tukwila sockets, and Intel is not going to rejigger the architecture so much that code running on prior Itaniums needs to be recompiled to run acceptably.
And, after that, comes the "Kittson" Itanium. Exactly when and exactly what this chip will have in it is still a mystery--even to Intel, whose engineering teams are right now beginning to define its functions.
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