Dual-Core "Montecito" Itanium Chips Launched Today

Published: July 18, 2006

by Timothy Prickett Morgan

Today is the big day. The bigwigs from Intel and its high-end server partners will rally in San Francisco to formally launch the "Montecito" dual-core Itanium processor, which will apparently be called the Itanium 9000 series.

In previews in 2005, Intel has said that the Montecito chips would have approximately twice the performance of the current "Madison" Itanium processors, which run at 1.6 GHz and which have up to 9 MB of on-chip cache to boost their performance. Like Madison, the Montecito chip is expected to run at 1.6 GHz. The specs of the chip and internal benchmarks showed that the Montecito chip could scale to 2 GHz or higher, but for some reason--most likely due to the fact that Intel's server customers and, in turn, commercial enterprises, are balking about the amount of heat the Montecito chip releases when it runs at faster clock speeds--the chip will debut at the same speed as Madison and yet still deliver that 2X performance boost. It is also possible that the Montecito chips have very low yields at the higher clock speeds; a chip with 1.72 billion transistors is going to be hard to make at any clock speed, and finding a chip with no smudges on it and that can cycle up to 2 GHz might be a bit of a challenge, even for Intel. IBM is apparently experiencing similar woes with its Power5+ dual-core chips, which were supposed to scale to 3 GHz or higher but which are expected to come in at 2.1 GHz and 2.3 GHz in a few weeks.

Each Montecito core has 16 KB of L1 data cache, 256 KB of L2 data cache and 1 MB of L2 instruction cache, plus 12 MB of L3 cache. Intel is not unifying the L2 or L3 caches, as it could have done and probably will with future chips. Each Montecito core will two virtual threads, enabled by HyperThreading, yielding four virtual threads per chip socket, which is four times that of the Madisons, which only have one physical thread per socket. Last October, when Montecito was delayed yet again, the company threw out the 667 MHz front side bus that was expected for the high-end Montecito part, along with its "Foxton" speed boosting technology. The Montecitos as delivered today are expected to have 400 MHz and 533 MHz front side bus speeds. They will also have Intel's VT hardware-assisted virtualization electronics and the co-called "Pellston" error correction technology, and DBS power management features.

Montecito has been a long time in coming, and could significantly bolster the Itanium's stature in the server space--at least at the high end of the market, where RISC processors still dominate and have many of the same error-correction and virtualization features. Montecito was originally supposed to come to market at the end of 2004, then was pushed to mid-2005, then out to mid-2006. The cumulative delays in Itanium conservatively come to around three years, and it would be very interesting to see what might have happened if these delays had not happened. But they did, and you can't get a do-over in the IT business. However, there's still plenty of room for Montecito in the server business, and it is a better chip than Madison, which is what counts.