Intel Aims Dual-Core Itaniums at RISC, Mainframe Servers

Published: July 25, 2006

by Timothy Prickett Morgan

After about 18 months of delays and having some features stripped out of it and its clock speed reduced, Intel has nonetheless been able to get its dual-core "Montecito" Itanium processors, dubbed the 9000 series, out the door of its chip fabs and moving into high-end machines from key players in the enterprise server racket.

Intel hosted a shindig in San Francisco to launch the chip with Pat Gelsinger, general manager of Intel's Digital Enterprise Group, which creates chips and platforms for the laptop, desktop, and server markets that Intel serves with its Xeon and Itanium processors, and Kirk Skaugen, general manager of Intel's Server Platforms Group, and a whole host of partners on hand to tout the Itanium not only as a staunch rival to Sun Microsystems' UltraSparc and IBM's Power and mainframe architectures, but as a platform that is gaining ground on these platforms and seeing increased support from the independent software vendor community.

Because Intel wants to offer server makers a variety of Itanium chips with different speeds, thermal properties, and price points, there isn't just one Montecito chip, but rather six of them. They are all based on the flagship Montecito, which is the Itanium 9050 that runs at 1.6 GHz and has the full complement of cache memories activated. Each Montecito core has 16 KB of L1 data cache, 256 KB of L2 data cache and 1 MB of L2 instruction cache, plus 12 MB of L3 cache. Intel is not unifying the L2 or L3 caches, as it could have done and probably will with future chips. Each Montecito core has two virtual threads, enabled by HyperThreading, yielding four virtual threads per chip socket, which is four times that of the Madisons, which only have one physical thread per socket. Last October, when Montecito was delayed yet again, the company threw out the 667 MHz front side bus that was expected for the high-end Montecito part, along with its "Foxton" Speed Burst technology, which would have allowed the Montecito to kick it up into high gear for short bursts if the system had enough room in its thermals to allow it. The Montecitos, as delivered last week, have 400 MHz and 533 MHz front side bus speeds. They also have Intel's VT hardware-assisted virtualization electronics and the "Pellston" error correction technology, which is now called Cache Safe Technology. With Cache Safe, a bad transistor in that large 24 MB cache block (which accounts for the vast majority of the 1.72 billion transistors in the Montecito chip) can be isolated in the event that a two-bit error hits the cache. (Chip makers and server makers have long since figured out how to cope with a single-bit error, but a two-bit error can cause a machine to crash. Cache Safe is a recognition that with such a large cache, the odds of a two-bit error go way up, so you have to cope with it gracefully.)

All of these features are enabled in the chip despite the fact that Intel is making Montecito using a 90-nanometer process to make this Itanium family, which has a top thermal design point of 104 watts running at 1.6 GHz with full caches on. Imagine the shrink in physical size (down from around 300 square millimeters) and lower wattage that would be possible if Intel was using the same 65 nanometer processes to make Montecito that it uses to make its new "Woodcrest" Xeon DP chips, which also have two cores on a die.

The top-end Itanium 9050 chip has two cores running at 1.6 GHz and has the full 24 MB of L3 cache activated. It can run in machines with either 400 MHz or 533 MHz front side buses, and it costs $3,692, down 13 percent from $4,227 that it charges for the single core 1.6 GHz "Madison" Itanium with 9 MB of cache, and with a 2X increase in performance, the raw Montecito chip offers about 56 percent better bang for the buck. Better still, the top-end Montecito compares well with the Madison in terms of energy consumption, with the Madison 9 MB chip burning at 130 watts for only a single core. So customers moving to Montecitos can double their performance and cut their energy use by nearly a factor of three.

If you can get by with less cache (and presumably less performance, because a lot of the performance increase with the Montecitos comes from those very large L3 caches and the L2-L1 caches that they feed into), then Intel has the Itanium 9040, which runs at 1.6 GHz but only has 18 MB of L3 cache (9 MB per core); this chip costs $1,980. The Itanium 9030 runs at the same 1.6 GHz, but only has 8 MB of L3 cache (4 MB per core), and costs $1,552. The Itanium 9010 runs at 1.6 GHz as well, but has only 6 MB of total cache; it costs $696. If you want more cache but slightly less clock speed, you can go with the Itanium 9020, which runs at 1.42 GHz and has 12 MB of L3 cache (6 MB per core); it costs $910. And finally, the Itanium 9015 runs at 1.4 GHz, has only one core activated, has 12 MB of cache (6 MB per core), but has only the 400 MHz front side bus; it costs $749. This latter chip is best, perhaps, thought of as a modest upgrade to the Madison 9 MB.

Throughout their presentations at the launch event, Gelsigner and Skaugen kept the topic of the conversation away from the entire server business (which the X64 architectures from Intel and AMD dominate in terms of shipments), and pitched the Itanium chip as an alternative to RISC architectures and mainframes, which they called proprietary (as most people do). In an interview after the event, Skaugen said that "the lesson is simple: standards-based computing wins. We are seeing significant migration off proprietary platforms. Choice of operating systems, choice of platform provider, and choice of applications wins." Intel said that it has more than 8,000 applications certified on the Itanium chip, from over 1,000 software companies. "Obviously, companies would not be investing in the platform if they didn't see the value in it," said Gelsinger in his presentation, citing the long list of "name-brand marquee applications" that were running on the Itanium. Other sources at Intel said last week that the company hopes to have over 10,000 applications on Itanium by the end of the year. It is interesting to remember that at its peak, the Sparc/Solaris platform had about 12,000 applications on it. With the applications base growing and the market finally getting a decently performing, reasonably inexpensive Itanium chip to market (at least for an enterprise-class server), Intel and the server partners who support Itanium (and who do not include IBM, Sun, or Dell, who were all enthusiastically behind Itanium a decade ago when it looked like Intel would sweep the world clear of X86 chips and replace them with Itaniums) are quietly optimistic about their prospects going forward.

To demonstrate how well Itanium is doing, Intel has been citing quarterly statistics from IDC, comparing Itanium-based server revenues against Sparc-based and Power-based server shipments across all vendors. In early 2003, Itanium revenues were at around a tenth of those of Sparc and Power lines. By the middle of 2004, it was up to around 20 percent of these platforms, and by the middle of last year, it was up in the 30 percent range. As of the first quarter of 2006, according to IDC, the revenue from Itanium-based machines was 42 percent of that from Power-based servers and 45 percent of that from Sparc-based servers. And in Japan, Itanium sales have already surpassed those of Power and Sparc.

If these numbers are indicators of future trends, then the first $5 billion in sales and 99,000 systems that have been shipped since Itanium first came to market may have been the difficult numbers to hit. The next $5 billion might be a little easier, and come a lot quicker, too. Whether the Itanic haters like it or not, Itanium will get its share of the $28 billion enterprise server market, even if the shipment numbers are not high compared to X64 platforms.

Intel has shipped thousands of Montecitos to key customers and server makers already, and expects vendors to qualify their platforms for the Itanium 9000s and begin shipping them starting in mid-August and ramping up through September. We'll be going into them, each in their turn, as well as doing price/performance analysis and looking at Itanium boxes as a platform on which to run ported mainframe workloads.