Intel Talks Up Larrabee X64-Based Graphics Engine

Published: August 5, 2008

by Timothy Prickett Morgan

Chip maker Intel, seeking to rub salt into the wounds of rival Advanced Micro Devices and its ATI graphics chip subsidiary and to get the X64 architecture chasing some pretty high-end visualization workloads in supercomputers and perhaps in game consoles if IBM is not careful, is this week providing some insight into the forthcoming "Larrabee" family of X64-based graphics engines.

Doug Carmean, the chief architect of the Larrabee graphics processor, and a team of Intel and academic researchers involved with the project will present a paper at the SIGGRAPH 2008 computer graphics and visualization trade show in Los Angeles on August 12, lifting the veil a bit on the Larrabee project, which Intel has hinted a lot about to try to drive AMD nuts in the wake of the expensive and perhaps at this point dubious acquisition of ATI two years ago when AMD looked a lot stronger and Intel looked a lot weaker. Because Larrabee is not slated to be a product until 2009 or 2010, Intel is going to keep some of the secrets about the product to itself for a while yet and just give AMD some grief as it sorts out its graphics processing plans, much as IBM and nVidia have done to position their products against Intel's future chips.

IBM, oddly enough, might have the most at risk, particularly if Intel can pitch a combined Core and Larrabee product line to game console makers Sony, Nintendo, and Microsoft, which all use a variant of IBM's Power processors but which could probably be convinced to move to X64 chips and associated GPUs if the numbers work out for future generations of their products. Such a move would remove billions of dollars in sales a year out of IBM's coffers, thereby pulling the financial rug out from underneath the commercial Power-based processor business. The fact that IBM makes these game console chips as well as millions of embedded processors a year for myriad devices means that it can keep its chip factory in East Fishkill, New York, running at capacity, making the economics all work out. If IBM had to depend on server revenue to prop up Power processors, it would be in a real bind because of the relatively low volume of Power4, Power5, and now Power6 chips it needs for its own consumption.

The Larrabee chip, as it turns out, is a derivative of the old Pentium P54C from the dawn of time, which means it has a short and less complex pipeline than more recent variants of the Pentium and follow-on Core microarchitecture. Larrabee is expected to have a two-issue, five-stage pipeline and offer four threads per core using an as-here-to-fore not announced variant of HyperThreading simultaneous multithreading, which Intel has always restricted to two virtual threads per core so far in its history. Each Larrabee core will include an in-order X64 scalar core (which means it is an X64 scalar core with 64-bit memory extensions). Each core also has a vector math unit that is capable of processing 16 32-bit floating point operations per clock cycle, and the scalar and vector units have their own sets of registers that in turn hook into L1 data and instruction caches (which are expected to be 32 KB each). The Larrabee architecture has one 256 KB L2 cache on the chip, but this cache is segmented so each core gets its own subset designated for it while also allowing each core to read the segments directly linked to each of the other cores and also--significantly--allows for data to be replicated quickly between core segments for parallel operations. Based on the block diagrams in the paper being presented at SIGGRAPH, the Larrabee cores are linked to each other by a ring bus (512 bits in two directions around the loop of cores), and the chip has two memory controllers, a texture logic unit, a fixed function unit, a system interface, and a display interface. The chip also supports the IEEE standards for single-precision and double-precision floating point math, as it would have to.

What Intel wants to stress--and what software developers are surely going to love to hear--is that Larrabee is a complete X64-style core: It has context switching and pre-emptive multitasking, virtual memory and page swapping, and fully coherent cache memories across the memory hierarchy in the chip. I am not certain if that means Windows and Microsoft Word will run on it, but Intel sure wants to imply that they will. The point is, if Intel can do supercomputing applications and graphics and visualization applications on a variant of the architecture that also runs most of the Windows and Linux workloads of the world, then the days of exotic non-X64 instruction sets might seriously be numbered. The point is, you can use the same development tools on Larrabee as you use on a regular Core chip and still get the benefit of parallelism and heavy duty math and rendering.

Intel is not telling anyone how many cores are in the Larrabee chip, but the presentations Intel will show for the chips doing various graphics rendering jobs show the core count ranging from two to 64. Those tests are showing pretty linear scaling up to 32 cores, and as things often do in the computer business, Larrabee shows diminishing returns with 40, 48, 56, and 64 cores on many workloads. (On some, though, there is still linear scaling.) The consensus out there on the Internet this week is that Larrabee will have 24 to 32 cores, and my guess is that Intel will make whatever someone will pay for so long as the yields on the chip are not too poor. Intel is not yet talking performance with any specifics, but depending on the core count and clock speed, a single Larrabee package with dozens of cores should be able to handle multiple teraflops of raw number-crunching performance. That's not too bad for something that will be implemented in 45 nanometer chip-making processes and probably be about the size of a plain, old Core chip in a laptop.

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