Intel Fleshes Out Server Chip Plans for Post-NetBurst Era

by Timothy Prickett Morgan

At the Intel Developer Forum last week in San Francisco, company executives revealed the processor roadmaps for 2006 and 2007 for its server chips and related platforms as it moves away from the NetBurst microarchitecture at the heart of its Pentium and Xeon chip families and toward a more power-conscious and as-yet unnamed future microarchitecture.

Intel divulged many of the names on its server roadmaps at the spring IDF, but the company has been making some tweaks even before the current IDF show, and it talked a bit about the future processors in the Xeon line not based on the NetBurst architecture, too. This is the first time Intel has discussed this new architecture, which essentially ditches the 31-stage "Prescott" Pentium 4/Xeon core and replaces it with a "converged core" that mixes Pentium M and NetBurst core features.

This new laptop core, called "Merom," has a desktop variant called "Conroe," both of which are expected to be available in the second half of 2006. Like the Pentium M chip, neither of these processors nor their Xeon DP server relative, known as "Woodcrest," will have HyperThreading simultaneous multithreading, which is a bit surprising considering all the trouble Intel went into creating it, but, then again threads are less of an issue on desktops and entry servers than power consumption these days. Intel is trading two virtual threads in a single chip for two cores in a single socket, and the time when dual-core Pentium and Xeon DP chips will have four threads per socket is destined for a short history.

This HT feature, which provides two virtual threads to an operating system, is one of the reasons why the Pentium 4's instruction pipeline grew from 20 stages back when Pentium 4 was first introduced to 31 stages in the current chips. The deeper the pipeline, the more work a chip can do, and when you add HyperThreading, a deeper pipeline can boost performance by about 20 percent or so in the Intel chip family (IBM gets more like 35 to 40 percent with its version of SMT). The Merom/Conroe/Woodcrest chips will all be dual-core processors (not just two Pentium 4 or Xeon chips slapped into a single socket) and will apparently have a much more streamlined 14-stage pipeline, according to reports, which means the new architecture has to be pretty efficient to get good performance. But assuming Intel can do that, what it also means is that these future chips will consume less electricity and throw off less heat. The Conroe chip might throw off a maximum of 65 watts, compared to the 95 watts of a Pentium 4, and Woodcrest could be as low as 80 to 85 watts, compared to 110 watts for the fastest Xeon chips on the market today.

Jason Waxman, director of marketing for Intel's Server Platform Group, says that with the Woodcrest chips, Intel was focused on performance per watt and performance per watt per square foot of floor space, not just performance, as the guiding metrics. He says Woodcrest, which will ship in the second half of 2006, would offer a performance boost over the dual-core "Dempsey" Xeon DP processor due in the first quarter of 2006 in two-socket servers--he would not say how much--but says that more importantly, the new cores at the heart of the Woodcrest chip would allow it to deliver a 40 percent increase in performance per watt. (My guess is watts goes down 30 percent and performance goes up 10 percent per socket.) Woodcrest will be implemented in a 65 nanometer chip making process, which means it will be a lot smaller than the current Xeon DP processors. This would usually mean more cache and faster clock speeds are possible. But exactly how Intel will boost performance over the Dempsey dual-core chips is unclear. Considering that Woodcrest has a shorter pipeline, which implies Intel can't just jack up clock speeds, and lacks HyperThreading, which shaves about 20 percent off chip performance, this is something of a mystery.

As Intel divulged a week ago, it has been working on a "Paxville" dual-core Xeon MP processor for next year, and it has decided to make a Xeon DP variant of Paxville available on servers that use the "Lindenhurst" chipset that was created for the current "Irwindale" Xeon DPs, which are 64-bit chips with HyperThreading that have 2 MB of on-chip cache. The Paxville Xeon MP was originally slated for the first quarter of 2006, and Intel is moving it up in a response to competitive pressures from Advanced Micro Devices, which has been shipping dual-core Opteron chips for servers for months. The Lindenhurst chipset has a limit of 16 GB of main memory and has a shared front side bus for those two cores, so the Paxville Xeon DP chip is not going to provide the kind of performance boost that Intel is promising with the Dempsey Xeon DP chip in the first quarter of 2006. The Paxville MP chip will ship after the Paxville DP chip, and both before 2005 ends. Exactly when, Intel is not saying.

Dempsey, also a dual-core chip that still uses the NetBurst architecture, will support fully buffered DIMM main memory and will have independent front side buses for each core. Waxman won't say what the bus speeds will be, but he did say that together the buses would have three times the bandwidth (if you do the math, that's a 50 percent increase in bus speed per bus compared to Irwindale, which means each bus is running at 1.2 GHz if Intel keeps the bus width the same, yielding an aggregate bus bandwidth of 19.2 GB/sec. That's a lot of bandwidth, which you would expect for a box that has for threads per socket. And the "Blackford" chipset used with the Dempsey Xeon DP chip will support up to 64 GB of main memory, four times as much as the 16 GB of memory supported in the Irwindale/Lindenhurst machines.

Waxman said that the Dempsey servers, which are called the "Bensley" platform by Intel, would offer about 1.75 times the performance of the Irwindale platform and 2.5 times the bandwidth, while the Woodcrest platform would offer 3.5 times the performance per watt of the Irwindale platform. (A little more oomph than the Dempsey setup, a lot less power.)

While changes are a-foot in the Xeon DP space, change takes a lot longer in the Xeon MP space. The single-core "Potomac" and "Cranford" Xeon MPs are just now getting rolling after being launched earlier this year, and with the dual-core Paxville Xeon MPs coming out early next year for the Intel 8500 chipset, that's about all the excitement the high-end server market can take. (All of these chips are made in 90 nanometer processes.)

Looking ahead, Waxman says in the first half of 2006, Intel will enhance the bus in Paxville, boosting the speed of the dual front side buses from 667 MHz to 800 MHz. In the second half of 2006, the dual-core "Tulsa" Xeon MP rolls out, implemented in a 65 nanometer process. The news today is that Tulsa will have two 8 MB L3 caches (one for each core) and will have a whopping 1.3 billion transistors on it, almost as large as the forthcoming "Montecito" Itanium 2 chip due at the end of 2005 or early 2006. The Tulsa chip will add Virtualization Technology (VT, for hardware-assisted instruction set virtualization) and Pellston Technology (PT, for on-chip error correction) to the existing HyperThreading (HT) features.

After Tulsa comes "Whitefield," which is based on the Merom/Conroe/Woodcrest core. Because Intel says it is a multicore chip, everyone expects it to have four cores. The platform for Whitefield is called "Reidland," and its chipset was not named. There is a kicker to Whitefield called "Dunnington," which will plug into the same Reidland platform.

On the Itanium front, Waxman says that Montecito is on track. All Intel would say about Montecito, its first dual-core Itanium and its first Itanium to have HyperThreading, is that it would offer about 2.5 times the performance of the current 1.6 GHz/9 MB single-core "Madison" Itanium 2 chips, have more than three times the front side bus bandwidth (two buses running at 667 MHz compared to one running at 400 MHz), and burn about 100 watts per socket compared to 130 watts with the Madisons (a reduction of about 20 percent). Montecito is expected to run at between 1.6 GHz and 2.2 GHz, and has two 12 MB L3 caches per core, and as far as anyone knows, they are not shared caches.

In other Itanium news, Intel confirmed that the future "Tukwila" Itanium, due about 2007 or so, would indeed have four cores and would employ a new architecture. This is the Itanium chip that will plug into the same Reidland Xeon platforms that are being called "Richford" when an Itanium chip plugs in. Tukwila will have HyperThreading, by the way, because those extra virtual threads mean something to customers deploying databases on Itanium iron. While this is true, the fact is Intel just retrofitted it onto Montecito, and taking it out in the Tukwila design would probably cost as much as putting it into Montecito in the first place. Considering that Windows can only handle 64 threads, a four-socket Tukwila box will be maxxed out on the thread count, which means Microsoft (and indeed other operating system suppliers) had better get their operating systems tweaked to support more threads. Because more threads are indeed coming than they can now use.

And while Itanium may not have come close to meeting its initially lofty goals, Pat Gelsinger, general manager of the Digital Enterprise Group that creates Intel's chips and platforms, said in his keynote that shipments of Itanium chips were up 170 percent in the first quarter of 2005 from the prior year's quarter. That is decent growth, and it is possible that it could accelerate as new OEM partners bring the Itanium kit to market.