Intel Pushes Out Itaniums, Replaces Future Xeon MPs

by Timothy Prickett Morgan

If you are a server maker or a server buyer who is anxiously awaiting those dual-core "Montecito" Itanium processors from Intel, well, you are going to have to wait a little longer to get your hands on one of those chips. Intel last week quietly pushed out the delivery date for the Montecitos to sometime in mid-2006, which had the cascading effect of pushing out the rest of the Itanium roadmap as well. But, as if to make up for it, Intel moved forward some new bus technology for the future Xeon MP server line.

According to William Giles, a spokesperson for Intel, the company started briefing server makers about the changes in the roadmaps this week. Because of unspecified issues with the dual-core Montecitos (which seem to have more to do with yields and the functionality of some new features if you read between the lines of PR-speak), the Montecito chips that were due to start shipping at the end of this year or early next year are going to be ready from Intel in "mid-2006." An Intel-ologist interpreting this would expect this to be sometime between the end of May and the first of July. This mid-2006 date is a far cry better than if Intel had said "summer of 2006," because the IT industry--and chip makers in particular--have a summer that sometimes runs well into October. So that is the good news.

Giles also added that Intel remained committed to its public statement that it would be delivering Montecito chips that would have approximately twice the performance of the current "Madison" Itanium processors, which run at 1.6 GHz and which have up to 9 MB of on-chip cache to boost their performance. That has not changed, even though the Montecito chip has, once again, been pushed out. Several roadmaps back, it was due in mid-2005, and before that, the end of 2004.

According to preliminary benchmark tests, Intel can get this 2X performance boost by sticking to a 1.6 GHz clock speed and without resorting to the use of its so-called "Foxton Technology," or FT, which allows a relatively cool Itanium to run in an over-clocked mode for a period of time to boost its performance. According to the rumor mill and some documents that we have seen, the dual-core Montecitos were capable of running at 2 GHz and even 2.2 GHz, and would have offered a lot more than 2X performance (but with a lot more heat, to be sure). So it is my guess that Foxton is not working right and that yields are low enough on the 90 nanometer process Intel is using that clock speeds can't be jacked up, so Intel is going to simply stop trying and deliver just what it promised: an Itanium that has about twice the performance.

The fact that the delivery of the chip--running at the low-end of the clock speed range and with Foxton turned off--is being pushed out six months seems to indicate that there is a big time yield issue. The chips do have two full Itanium cores and two 12 MB L3 caches on-chip, with 1.72 billion transistors. Each Montecito core has 16 KB of L1 data cache, 256 KB of L2 data cache and 1 MB of L2 instruction cache, plus 12 MB of L3 cache. Intel is not unifying the L2 or L3 caches, as it could have done. Each core will have two virtual threads, enabled by HyperThreading, yielding four virtual threads per chip socket. The 667 MHz front side bus that was expected for the high-end Montecito part has been tossed out the window with Foxton, Giles said, and the Montecito will only come with 400 MHz and 533 MHz front side bus speeds. The Montecitos will have "Vanderpool" VT virtualization features (but will no longer beat the Xeons to market with this feature), as well as "Pellston" error correction technology, and DBS power management features.

Because Intel needs about a year to roll out a new Itanium generation--and, as Montecito shows, sometimes a little more--the "Montvale" kicker to Montecito is now slated for some time in 2007 instead of the late 2006-early 2007 launch date from roadmaps earlier this year. The rumors--which Intel absolutely would not confirm--say that not only is Montvale not moving from a 90 nanometer to a 65 nanometer process, but it is losing quite a bit of clock speed, dropping from around 3 GHz to 2 GHz. This revamping and delay of Montvale, of course, pushes the multicore "Tukwila" Itanium out into 2008. (Somewhat humorously, Intel just won't come out and say that it is a four-core chip, apparently because it is more suspenseful this way, but we all think it is a four-core chip and considering how tough it has been for Intel to get a dual-core Itanium chip out the door, I can't imagine the woe of trying to do a six-core or eight-core chip. So let's just start calling it a four-core chip if that is what it is and stop being coy, OK?) If I had to guess--and I have to because Intel doesn't really explain anything--I would say that the yields on these monster dual-core Itaniums are low in the 90 nanometer process and that Intel is anticipating even bigger problems with the 65 nanometer process that Montvale used to depend on and that Tukwila still does.

The ironic bit of all of this is that Intel had originally planned to put a dual-core Itanium in the field in 2006, code-named "Chivano," and redid its roadmap to get a dual-core Montecito chip out the door in 2004 after pushing Montecito out from its original single-core 2003 delivery date. After all the roadmap changing, nothing changed. Those changes were aimed at getting the Itanium chip to parity with IBM's Power processors--something Intel still sorely needs to do to keep all of its Itanium server customers happy. They can't be happy with the delay--that is for sure. The fact is, all Intel has done since the Madisons were launched in July 2003 was boost the clock speed by 100 MHz, triple the L3 cache to 9 MB, and boost the bus speed to 533 MHz. This is not enough when Opteron and Power processors are doubling in performance over the same time frame.

The news is somewhat brighter over in Xeon MP land. According to Giles, Intel was not too pleased with the performance boost that it was going to be delivering with the "Reidland" platform and its "Whitefield" Xeon MP processor. So, it threw it out and started from scratch. Now there is a new platform called "Caneland," and a new chip called "Tigerton," and this new platform-chip combo (using an as yet-unnamed chipset) will come out in 2007 instead. While Giles said this new Xeon MP chip and platform will have a lot of new features to boost performance more than the Reidland platform and Whitefield chip would have, he would only talk about one of the features, which is called the Dedicated High Speed Interconnect.

Those of you who are familiar with Advanced Micro Devices's Opteron processors and their HyperTransport links between the processor, I/O, and integrated memory controller--don't get too excited. Intel is not remaking the Xeon MP in the Opteron's image. The Tigerton Xeon MP will have four high-speed buses, one for each chip socket on a Xeon MP cell board or motherboard. Right now, all of the four sockets in the Xeon MP share a single front side bus, so giving each socket its own bus should reduce contention in the system. But this Dedicated High Speed Interconnect only connects the Xeon MP CPU to the chipset on the motherboard. Memory still talks to the chipset, not directly to the CPU. This is not a clone of HyperTransport, and Giles said that the Tigerton chip will not have an integrated main memory controller on the chip; Intel plans to make up for memory latencies by having large caches on chip. By the way, the Tigerton chip appears to be a dual-core chip, so each core will still be sharing a single Dedicated High Speed Interconnect.

The one thing that seems to have also been sacrificed as part of this roadmap change is the converged Xeon-Itanium server platform that was scheduled for delivery with the Reidland platform in 2007. Giles said that the Tukwila Itanium chips will still support this converged platform, but ironically, Intel is not yet saying what Xeon platform it will be converged with. Apparently it is not the Caneland/Tigerton combo.