AMD: Native Quad Core Opteron Will Best Intel Quasi Quads

Published: February 1, 2007

by Timothy Prickett Morgan

The price war underway between rivals Intel and Advanced Micro Devices in the arena of server and workstation processors is also a technology arms race. Advances in technology are what, in fact, allow each side to continue to cut prices--often, as the past quarter has shown, to the detriment of the bottom line. But, war is war, and once you are in it, you have to be in it to win it.

Like so many technological warriors in the past, AMD finds itself between product lines and talking up a future technology that it says will be better than the current technology offered by its rival.

Specifically, AMD is telling anyone who will listen--and plenty of people are listening to AMD these days, unlike several years ago when the Opteron did not look like such a safe bet--that its future quad-core "Barcelona" Opteron processors will just blow away the quasi quad-core "Clovertown" Xeon 5300s from Intel. Rather than putting put a single piece of silicon with four processor cores and integrated caches, Intel has taken two of its dual-core "Woodcrest" Xeon 5100 processors and put them in a single chip package so they can both run in a single CPU socket; this is somewhat mockingly called a quasi quad-core chip, because it offers the benefits of four cores--more processing threads and more performance per watt--that a real quad core chip does. For customers who need lots of threads to support their applications, the Clovertown Xeon chips offer much better bang for the buck than the Woodcrest Xeons do--and they make the current Rev F Opterons look underpowered and hot by comparison, too.

But, according to Kevin Knox, vice president of AMD's worldwide commercial business--which means servers and workstations--the future Barcelona Opteron chips are not just two Rev E cores put onto a single piece of silicon, much less two separate chips jammed side by side.

"This is more than just a quad core chip," says Knox. "We have done quite a bit of work, and this will be a major update for Opteron. The changes in the core and the caches are going to give us significant performance advantages."

AMD's dual-core "Santa Rosa" Opteron Rev F chips came out in mid-August 2006, several months later than expected, but offering support for faster and cooler DDR2 main memory and a slight performance boost compared to the Rev E Opterons. The Barcelona chips will plug into the same Rev F sockets as the dual-core chips, will have the same thermal characteristics as the existing dual-core Opteron 1000, 2000, and 8000 series of chips for one-, two-, and four-socket (and higher) servers. The current Opteron chips also come in standard, highly efficient (HE), and special edition (SE) variants, and this practice is expected to continue with the Barcelona chips, too, says Knox. The standard Opteron parts have a thermal envelope of 95 watts, while the HE variants run at a lower voltage and a lower clock speed, but have a thermal envelope of 68 watts. The Opteron SE chips run at a higher clock speed, and therefore they generate more heat--a maximum of 120 watts, as it turns out. These chips are for customers who absolutely need the highest performance available and who do not care about electricity usage or heat. (All of those thermal metrics include the heat generated by the on-chip DDR2 main memory controller; Intel's TDP measures do not include a memory controller, since this function is performed by external chipsets.)

One performance advantage that AMD is counting on, says Knox, is the faster data sharing that is possible between the cores and caches on the single Barcelona chip. Each Barcelona core will have its own L1 and L2 caches, and then the whole shebang will have, as many suspected, an L3 cache memory that will boost throughput into the cores from the outside world. This L3 cache will initially be 2 MB in size, but will grow over time if workloads demand it. This cache can also act as a conduit between the cores, so they can move data around as applications need it without going off the chip.

AMD has also quadrupled the floating point performance of the Opteron chip by moving to 128-bit paths in the pipelines that link out to the SSE execution units in the chip. AMD has also added a dedicated 36-entry scheduler for floating point units, which contrasts with Intel's 32-entry scheduler, which is shared between integer and floating point units. Knox says that on some number-crunching workloads, customers will see 80 percent performance improvement per core moving from the Rev F Opteron 2000 series to the equivalent quad-core Barcelona.

Another performance advance that AMD is counting on with the tweaks to the Barcelona chips is called nested page table acceleration, which is an extension to the hardware-assisted virtualization feature known as AMD-V (and formerly known by its code-name, "Pacifica"). AMD-V made its first appearance in the dual-core Rev F chips last August, and it does in hardware some of the things that hypervisors had to do in virtualized machines, but in software. Software, of course, runs a lot slower than hardware. Knox says that the nested paging features adding to AMD-V will allow "near native" performance on applications that run atop of virtualizing hypervisors.

AMD is not being specific about how general workloads will perform when moving from the dual-core to the quad-core Rev F chips, but is does say that it can beat Clovertown by 42 percent on floating point workloads.

The Barcelona chip is implemented in a 65 nanometer copper/SOI chip process, and is a shrink from the current 90 nanometer copper/SOI process AMD is using now. Because of the additional cache memory and the doubling of the cores, AMD had to cut back a bit on the clock speed in the Barcelona chips to make it all stay in the same thermal envelopes. Intel had to do the same thing when making the Clovertown chips from the Woodcrests--and for exactly the same reason.

Knox says that AMD is working "fast and furious" to make sure the Barcelona chip is ready for its mid-2007 introduction. AMD executives would not be more specific about the launch date--especially after the dual-core Rev Fs were delayed by two months last summer. Hopefully for AMD, there will not be another similar delay with Barcelona.

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