IBM Divulges Details on Future "Cell" Processors

by Timothy Prickett Morgan

IBM and its partners, electronics makers Sony and Toshiba, this week announced some of the details of its forthcoming "Cell" processor at the International Solid State Circuits Conference in San Francisco. The Cell chip is generating a lot of excitement for a lot of different reasons, but particularly because its architecture embodies the ideals of cyberpunk novels from two decades ago.

Back in November, when IBM knew it was going to file its ISSCC papers, it tried to control and stoke the interest around the Cell processor, an exotic variant of its 64-bit Power processors, by putting out just enough information to get a bunch of stories in all the major consumer and trade press, but leaving enough unsaid so we would all come back and write this story again. As you can see, this strategy works.

If you like hardware--and I do--then you will probably want a cluster of machines based on the future Cell processors as your desktop, your HDTV, your home server and entertainment center, and your car dashboard. And if you don't want Cell processors everywhere, then you may not have a choice, because this is exactly what IBM, Sony, and Toshiba are spending hundreds of millions of dollars to build. Based on what little information I have seen, I definitely want systems with the attributes that IBM, Sony, and Toshiba are weaving into the Cell processor and its grid architecture.

Whether or not Cell, which has been in development since 2001, will be disruptive to the hegemony of the X86 processor in the desktops and servers of the world remains to be seen. But Cell, if it works as advertised, certainly looks poised to take over even more embedded markets than the 32-bit and 64-bit variants of the Power chip currently have. As I said back in November, the Cell chip embodies a deadly serious architecture, and while IBM will not admit that it wants to take a run at the X86 on the desktop and in the server, there is clearly a chance for that given the widely held belief that Linux will become a dominant platform and the slight chance that Cell could even run Windows at some point. In the meantime, until it proves itself, Cell will occupy a position slightly more outside of the IT market than Digital Equipment Corp's Alpha RISC processors from a decade ago. I liked Alpha then (for technical reasons), and I like Cell now (for the same kind of aesthetic reasons). It will be up to history to decide if both of these chips were trying to solve problems and chase markets that are phantoms instead of reality. All I know is that the time machine needed to prove Cell's success also needs the kind of computing power and grid-capabilities that IBM is talking about in the Cell architecture.

The Cell chips are going to pack a wallop when it comes to number-crunching power. Each Cell chip has a variant of IBM's 64-bit Power processor core surrounded by what are called Synergistic Processor Units (SPUs), which is a funky way of saying pipelined floating point processing units with their own local memory. Processors already have floating point units, so this is not a big deal. The Power4 and Power5 processors from IBM, for instance, have two floating point math units, each capable of processing two floating point instructions per clock cycle. The difference with the Cell chip is that these SPUs will occupy a huge amount of real estate on the 221 square-millimeter chip and account for a large number of its 234 million transistors. The three Cell partners want this massive amount of computing power so they can use the chips in servers and workstations from IBM as well as in any consumer device that is manipulating streaming video and audio in real time. No matter where you use Cell, you need to do a lot of calculations for high-resolution images and high-fidelity sound.

The core at the heart of each Cell chip will be a derivative of either the Power5 or PowerPC 980 core. The former implements simultaneous multithreading (SMT), giving software two virtual threads to play with for each single thread. The PowerPC 970 did not have SMT support, and it did not have support for the special memory tags necessary to support the OS/400 operating system from IBM; PowerPC 9XX line of chips can run AIX, Linux, and MacOS, however. The Cell core will also be equipped with the VMX vector math unit developed by Motorola and used by Apple with some success to differentiate its various desktops and Xserve servers from the X86 competition. The PowerPC 970 chip had VMX support, and it seems more likely that IBM added SMT to the PowerPC 980 and put that core into the Cell rather than adding VMX to a stripped down Power5. The Power5 and future Power6 chips have lots of stuff that the Cell doesn't need (such as support for symmetric multiprocessing and memory tags for OS/400), so it seems unlikely that Cell is based on Power5.

The Cell chip is architected more or less as I guessed back in November. Each core in the labs is running at over 4 GHz, and each SPU seems to be a variant of the Floating Point Units (FPUs) already used in the Power chips, with four FPs per SPU. With eight SPUs per Cell chip (that's 32 FPUs) it can deliver 256 gigaflops at 4 GHz. The Cell chip has a direct memory access (DMA) controller all residing on a set of Rambus serial links between the elements of the chip. IBM said this week this interconnect bus will deliver 96 bytes per clock, and other sources have said it will run as high as 6.4 GHz. The chip will have a total of 2.5 MB of memory, including 512 KB of L2 memory for the Power core and 256 KB of L1 cache each for the eight SPUs. The architecture of the Power core plus its VMX vector processor is such that the Power core seems to see the SPUs through the VMX. The chip will also have hardware-assisted virtualization, which will allow a single Cell (or multiples lashed together through on-chip interconnections) to run multiple operating systems simultaneously. The Cell architecture includes power management features that allow parts of the chip to be activated or deactivated as needed.

IBM will start production of the Cell chips between now and the end of June, if it keeps on schedule, at its chip fab in East Fishkill, New York using its new 300mm, 90 nanometer copper/SOI process. Last fall, IBM and Sony said they were developing a workstation based on Cell chips, which is the first product IBM will ship based on Cell. This workstation will apparently be aimed at game programmers and digital rendering houses. Sony also plans a 2006 launch of home servers and HDTVs that use the Cell chips, and will also use the chips in its computer entertainment center, which represents the merger of TV and PC with broadband networks and wireless devices. The Cell chip will eventually be at the heart of the PlayStation 3 game console, too. Last year, Sony paid IBM $325 million to help IBM work out the kinks in the 65 nanometer chip processes it is developing and to gain the capability to make the Cell chips in its own 300mm fabs in Nagasaki, Japan. Toshiba has said it will have a diverse line of products, beginning with an HDTV in 2006, that will be Cell-based.