IBM to Ditch SRAM for Embedded DRAM on Power CPUs

Published: February 15, 2007

by Timothy Prickett Morgan

According to a presentation that chip designers from IBM made this week at the IEEE's annual International Solid State Circuits Conference in San Francisco, the company has perfected a way to embed Dynamic RAM, or DRAM--the normal kind of main memory used in computers--into microprocessors rather than having to resort to the much more transistor-intensive Static RAM, or SRAM, commonly used in on-chip L1 and L2 cache memories.

IBM has been testing the embedded DRAM concept for microprocessors for a while, and in fact used embedded DRAM in the variants of the stripped-down PowerPC 440 cores that are the heart of the processors used in its Blue Gene line of massively parallel supercomputers.

But now IBM researchers say that they have perfected the technology to the extent that IBM plans to use embedded DRAM in future 45 nanometer processors that will be built using a silicon-on-insulator process that is similar to that which IBM has been perfecting since SOI was introduced way back in 2001 using a 130 nanometer process.

While SRAM is very fast--allowing data to be fetched from it in 1 nanosecond or slightly less in some cases on a CPU chip--it takes six times as many transistors to store a bit of data in SRAM as it does on DRAM. (This is one of the reasons why DRAM is relatively cheap and can be mass produced in 1 GB quantities.) As transistors have shrunk in size, vendors have had to keep their chips in balanced performance by adding more and larger SRAM L1 and then L2 caches--which means that the caches dominate the chip surface area given chip. This is especially true of designs like Intel's Itanium, with its front bus architecture, which is relatively slow and therefore needs a big cache to boost the overall performance of the chip. IBM's Power line of chips have very fast I/O in the cache memories on the chip, so the caches can be smaller; the architecture also incorporates an off-chip L3 cache, which helps make sure the right data ultimately ends up down in the L1 caches and then gets crunched by the CPU.

DRAM is also not as subject to a phenomenon called current leakage, which in plain English means the wires are so thin that the electrons that run around in the circuit can pop out of the wires and into areas where they do not belong. Considering that all a chip does is flip bits based on the movement of electricity, corralling all of these electrons is a big deal.

The embedded DRAM technology that IBM is working on for future microprocessor chips will come to market in 2008 using a 45 nanometer process that mixes all the goodies IBM can bring to bear--copper wires, SOI, low-k dielectric, and the new high-k gating technique it talked about a few weeks ago. The test chip that IBM is showing off at ISSCC this week is a prototype microprocessor using a 65 nanometer SOI process--the one IBM is using to make the future Power6 chip for servers and the current game console microprocessors based on the Cell chip and other PowerPC derivatives (in the case of the Xenon processor used in the Microsoft Xbox 360).

That prototype 500 MHz chip created by IBM was able to move data in and out of the memory in a random fashion in under 1.5 nanoseconds, which is a bit slower than SRAM--half as fast compared to the fastest SRAM on the market, in fact. But the embedded DRAM was considerably faster at dispensing data than normal DRAM, which can take almost 10 times as long to do the same task. Because DRAM has much fewer transistors and less memory leakage, IBM says it can cram three times as much DRAM cache on the chip, which will make up for some of the slowness of embedded DRAM compared to SRAM.

The overall effect of large on-chip caches, as Intel has demonstrated so well with the Itanium and its very large 12 MB L2 caches per core in the most recent Itanium 9000 chips, is to boost performance. The clock speed on the dual-core "Montecito" Itanium 9000 chips was at the same 1.6 GHz as the single-core "Madison" Itanium 2 chips, but the cache per core was increased by 50 percent and the bus speed was increased to get more data into those caches more quickly.

It will be interesting to see if other chip makers follow IBM's lead with embedded DRAM on processors, as they did with copper, SOI, and low-k technologies.

                     Post this story to del.icio.us
               Post this story to Digg
    Post this story to Slashdot