Sun Updates Sparc Processor Roadmap

by Timothy Prickett Morgan

Progress is perhaps the most important product in the computer industry, and while the ink on Sun Microsystems' the UltraSparc-IV announcement press releases was not even dry, the companies top techies were already talking up what future enhancements the company has in store for its indigenous processors. The details were a little scare, but the company believes that it can relatively quickly double the performance in its Sun Fire line with the "Panther" UltraSparc-IV+ kicker to the just announced "Jaguar" UltraSparc-IV.

The Jaguar chips are Sun's first dual-core processors and the first to offer multiple execution threads. The chips, which are available in a new Sun Fire Enterprise server line that was also announced last week, currently run at 1.05 GHz and 1.2 GHz, just like the fastest "Cheetah" UltraSparc-III processors that were the first generation of processors used in the Sun Fire server line. The Jaguars, like the Cheetahs, are manufactured by Texas Instruments using a 130 nanometer, seven-layer copper/low-k CMOS process. With two cores in Jaguars compared to the single core in the Cheetahs, the Jaguars offer roughly 1.8 times the performance on typical Solaris applications; those applications that have been tweaked to support multithreading (such as Solaris itself) may do even better. The Jaguar chip has an L1 cache in each core comprised of a 64 KB data cache, a 32 KB instruction cache, a 2 KB write cache, and a 2 KB prefetch cache. The chip also has 8 MB of L2 cache per core, the same as the Cheetahs. The Jaguar also implements a main memory controller on the chip, with support for up to 16 GB of main memory per four-chip (eight core) cell board. The whole shebang is composed of 66 million transistors and consumes 108 watts of power running at 1.2 GHz.

With the next-generation Panther chips, Sun and TI will be moving to a 90 nanometer copper/low-k/strained silicon process, which will allow it to do a few different things. The relative size of the circuits (in terms of their area) will shrink by half. Smaller circuits consume less electricity (since the distances between components is shorter) and can therefore be run at higher frequencies. Just moving from 130 nanometer to 90 nanometer processes should allow Sun to roughly double the clock speed on the future Panther chips compared to the new Jaguars. The smaller circuits also allow Sun to put more things on the chip itself. While Sun's top chip designers last week were promising to offer a large Level 3 cache memory for the Panthers--the first L3 cache Sun has ever put in a server, and an approach that Sun has maligned in the past as its competitors (mainly IBM) adopted three-cache heirarchies--it seems likely that Sun will try to move the current 16 MB L2 cache in the Jaguars on chip. On-chip caches of any type (L1, L2, or L3) are physically closer to the processors, which means they have lower latencies and can run faster than off-chip caches. This means for a given level of performance, a smaller on-chip L2 cache can provide the same performance as a much larger off-chip L2 cache. It would not be surprising to see Sun put two 2 MB or maybe even 4 MB L2 caches on the Panther chip thanks to the move to the 90 nanometer process.

In further chip news, Sun gave a code name to its "radical chip multithreading" processor family: the "Rock." It is hard to say if Sun is referring to a beefy wrestler, life insurance, or Alcatraz. Given what Sun is trying to do by shifting from monolithic processors with single threads running at high clock speed to processors with multiple cores and even more threads, all three referents make some sense.

In further chip news, Sun gave a code name to its "radical chip multithreading" processor family: the "Rock." It is hard to say if Sun is referring to a beefy wrestler, life insurance, or Alcatraz. Given what Sun is trying to do by shifting from monolithic processors with single threads running at high clock speed to processors with multiple cores and even more threads, all three referents make some sense.

The Rock processors will follow the "Niagara" processors, which will be aimed at entry and some midrange servers, to market, but Sun has not yet said when to expect them. These chips, along with the future dual-core "Gemini" kickers to the UltraSparc-IIi processors used in entry workstations and servers, are often lumped together under the "throughput computing" banner by Sun.

Sun is using the same 130 nanometer process to make the dual-core Gemini chip as it is using to make the new Jaguar UltraSparc-IVs. The Gemini chip is interesting in that it is based on a cut-down UltraSparc-II Blackbird cores, not the Cheetah UltraSparc-III or "Jalapeno" UltraSparc-IIIi cores. The Gemini chip has been sampling since late last year at 1 GHz and 1.2 GHz, and only dissipates 32 watts of power at the higher clock speed. The Gemini chip will support one thread per core and four instructions per thread, for a total of eight simultaneous instructions per chip; Gemini also has an integrated DDR1 main memory controller and a JBus system bus interface, just like the Jalapeno chip. The Gemini chip is pin-compatible with the Jalapeno chips, and its servers will be able to support one, two, or four of these dual-core processors for what amounts to a maximum of eight-way processing.

In the late 2005-early 2006 timeframe, TI will have a 65 nanometer process that will allow Sun to shrink its chips and crank-up the clocks even further on the UltraSparc-IV, if it needs to. This same process will be used to create the "Niagara" CMT processors, which will pack eight of the four-threaded simplified UltraSparc-II cores used in the Gemini chips onto a single piece of silicon. In Sun's roadmap, relative performance is being reckoned against the oomph supplied by the "Hummingbird" UltraSparc-IIi processor running at 650 MHz. Sun has said that it expects that the Niagara chips will provide about 15 times the performance of this baseline processor, and it UltraSparc-Iii. In the past, Sun has said that the third generation CMT chips, which are now known as the Rock family, will deliver 30 times the performance of this baseline. But raw performance is not the only thing of value with these future CMT designs, according to Sun. These chips are being designed not only to do commercial computing, but also to be reconfigurable so they can assist with helping manage network traffic in the servers that use them.

In further Sparc processor news, Sun says that it has nearly finished the designs on the UltraSparc-V processor as well as the Niagara chip. Both are expected to tape out and be sent to TI for the ramp up to manufacturing in the next few months. The "Millennium" UltraSparc-V processor, like the radical CMT designs, will be a configurable, multicore processor that can be used in one mode for multithreaded work and in another mode for workloads with few threads and a need for clock speed. The word on the street is that the UltraSparc-VI processor has been dropped from the Sparc roadmap, something we have not been able to confirm with Sun. Not much was known about the UltraSparc-VI, but Sun clearly thinks that many small engines on a single chip that can morph to fit workloads is a better design choice than trying to built bigger chips with ever-higher clock speeds. Given that TI is arguably Sun's biggest bottleneck when it comes to clock speed, this attitude may be one of necessity as well as philosophy. As for UltraSparc-V, the odds favor Sun and TI jamming up to four UltraSparc-III style cores onto the same chip, but the design could be considerably different.