But Wait, There's More

Intel Bites the Bullet: Xeon Gets 64-Bit Support

by Timothy Prickett Morgan

The conspiracy theorists are not always wrong. The future Xeon workstation and server processors from Intel that are based on the new "Prescott" core that was announced a few weeks ago do indeed have 64-bit memory extensions in them. With the launch of 64-bit Xeons, which will roll out in the next several months, server strategies based on Itanium and Opteron are put into a new light, if not called directly into question.

Intel made the announcement of the 64-bit extensions to the Xeon processors last week, during the opening keynote address by CEO Craig Barrett at the Intel Developer Forum in San Francisco. In referring to the 64-bit extensions, which were reportedly developed under the code name "Yamhill," Barrett called the extended Xeon "probably the worst kept secret in Silicon Valley history."

It is easy to laugh about this, but Yamhill is serious business, and the fact that rival Advanced Micro Devices had garnered two tier one server suppliers with its 32/64-bit Opteron processors (IBM and Sun Microsystems) and looked as if it was just about ready to close the endorsement of a third (Hewlett-Packard) seemed to have forced Intel's hand. Intel would have undoubtedly preferred that the industry would have wholly supported its 64-bit Itanium alternative after investing a decade and billions of dollars in that product line. But to not extend Xeon would be to let the AMD camel gets its nose under the Intel circus tent. It is better to have three processor product lines than have your two products lose business to a rival alternative that has many of the same benefits embodied in one product.

Barrett's presentation, like so many of them at IDF in the past, focused on the increasing digitalization of the world and Intel's position as a key supplier of circuits that power the convergence of computers, communications, and content. These speeches are not so much broken records to the 5,000 attendees of IDF as they are a great song that they love to hear over and over. Rather than just dive right into the 64-bit Xeon announcement, Barrett started from the top of its product line with big iron Itanium chips and worked down to the desktop, PDA, and cell phone devices which have Pentium and Xscale processors. Before talking about the 64-bit Xeons, Barrett stressed that Intel had sold over 110,000 Itanium processors to date and that it would at least double that number in 2004. (It was not clear if he meant Intel would sell 220,000 or more additional Itaniums or double the installed base to 220,000.) He said that over 50 OEM partners were pushing Itanium machines and that over 1,000 applications have been ported to Itanium.

"Lots of new capabilities will be coming for Itanium," he said, including dual and multiple core implementations, chip multithreading, improvements in cache memory reliability, PCI Express I/O, and better power management features that allow the Itanium processors to run at a cooler temperature.

And to make his point that the Itanium processors have a long life ahead at Intel, Barrett brought out the CEO and CIO of Morgan Stanley, the financial services giant based in New York, to swear their loyalty to both Itanium and Xeon. In 2001, Morgan Stanley began a project to migrate away from its RISC/Unix back end database and risk arbitration systems (which were apparently based primarily on Sparc/Solaris iron) to X86 servers running Red Hat Linux. Morgan Stanley said that over the course of the past four years, when this migration was taking place, it had quadrupled its trading volume to 1 million trades a day, but the amount of fees it could extract from each trade had fallen by a stunning 80 percent. The only way to stay in business was to radically cut the cost of each transaction. And while 32-bit Xeon servers offer low prices, for the kind of number-crunching and big database jobs that Morgan Stanley is running, Itanium, not Xeon, provided the best performance and, ultimately, the best bang for the buck.

According to Jeff Birnbaum, CIO at the Morgan Stanley, on the risk assessment financial applications it runs, the Itanium outperformed the fastest Xeons by a factor of 2.5 times, thanks in large measure to the floating point performance of Itanium. On database applications, where main memory makes a big difference in performance, the Itaniums could outpace the Xeons on a chip-for-chip basis by a factor of 3 to 10 times running Morgan Stanley's actual code.

This, of course, begs the question of how the 64-bit support in Xeon will change the cost/benefit analysis at the thousands of companies like Morgan Stanley who have already adopted Itanium as well as at the many millions of companies who have not yet bought 64-bit servers but who will in the coming years. It is hard to fathom how much the expanded memory means to the performance of entry and midrange systems, but it is critical for any enterprise class system. To put it bluntly, any 32-bit system has a maximum of 64 GB of main memory it can address, and that is simply not enough in a box that might have 16, 32, or 64 processors in a single system image sharing that memory. For big iron, its was either Yamhill or Boot Hill for Xeons, because companies would either have to jump to Itanium or hope that Opteron machines would eventually scale beyond their current practical eight-way limit.

The important thing to IBM and Dell, neither of which are very ardent supporters of Itanium, is that 64-bit Xeons have finally been announced. Exactly what HP feels about all of this is unclear, but it must be torn by its desire to see Itanium turn to its own advantage and its desire to sell inexpensive iron and win deals against all other server makers. Sun already supports a 32-bit version of its Solaris Unix environment on Xeon chips, and has recently adopted the Opteron as its 64-bit Solaris X86 platform. It will be interesting to see what the advent of 64-bit Xeons means for Sun's long-term server strategy and its relatively new commitment to AMD. Sun almost certainly will embrace the 64-bit Xeons, which could undermine its alliance with AMD.

Barrett said that the 64-bit extensions for the Xeon chips would ship first next quarter in the "Nocona" Xeon DP kickers to the current "Prestonia" Xeon DPs. The Noconas have the new Prescott cores that can access an 800 MHz front side bus, while the Prestonias have the older "Northwood" Pentium 4 cores. He also said that the 64-bit extensions to Xeon would ship in mid-2004 with the actual uniprocessor Prescott chips, and would debut in the high-end "Potomac" Xeon MP chips, which are aimed at four-way and larger machines, in early 2005.

It seems that the ability to access 64-bits in the Xeons will be determined by chipsets as much as by the chips. That means that the future "Grantsdale" chipset, which will begin shipping in the second quarter, is what really allows Prescott to do 64-bit computing. The Nocona Xeon DP chips are expected to support two chipsets, "Lindenhurst" and "Tumwater," dual-processor servers. It could turn out that while both chipsets will support PCI Express point-to-point I/O interconnections, DDR2 memory subsystems, and on-board dual Gigabit Ethernet links, one chipset could offer 32-bit processing on Nocona Xeon DP chips activated for 32-bit mode while the other chipset is for 64-bit mode Noconas. The different chipsets could turn out to be for workstation or server implementations and that they both support 32-bit and 64-bit modes. Either is possible. There only appears to be one chipset for the future Potomac chips, the "Twin Castle" chipset. That probably means that future Xeon DP and MP chips will be able to run in either 32-bit or 64-bit modes, like the Opterons can. This is what customers want.

The Nocona chip will run at 3.2 GHz, have 1 MB of L3 cache, and will sport an 800 MHz frontside bus. Nocona will be implemented in a 90 nanometer process, just like the Prescotts. The "Jayhawk" Xeon DP, due in late 2004 or early 2005, will be essentially the same chip, but with a higher clock speed and possibly a larger L3 cache. In mid-2005, Intel is expected to roll out a dual-core version of Potomac called "Tulsa," which will also plug into the Twin Castle chipsets. All five of these chips--Prescott, Nocona, Jayhawk, Potomac, and Tulsa--will support 64-bit processing.

Barrett said last week that over 5,000 developers, systems partners, and software partners have had access to the 64-bit Xeons and are working on ports and qualifications for their products. In a question and answer session following the keynote address, he said that the Intel Pentium and AMD Opteron processors had a different microarchitecture and therefore software written for one would have to be tweaked on the other. But it could turn out that Intel, which has a cross-licensing agreement with Intel, has simply implemented AMD's 64-bit methods from Opteron inside Xeon. In effect, 64-bit Xeons may turn out to be AMD inside. On the software front, Barrett said that Microsoft had been working for quite some time on the 64-bit Xeon support for Windows 2003, and said further that Red Hat, SuSE, and MonteVista Software would be rolling out versions of their Linux operating systems for the 64-bit Xeons. All four are expected to deliver their tweaked operating systems for 64-bit Xeons in the mid-to-late 2004 time frame. He didn't mention the SCO UnixWare or OpenServer variants of Unix for the X86 processors, nor did he say anything about Solaris for X86 or FreeBSD Unixes for Intel platforms, but I will be chasing down what the deal is with these as it relates to the 64-bit Xeon extensions. It will be very cold in Hades when HP considers porting HP-UX to Xeon-64 or IBM considers doing a port for its AIX.

Intel Draws More Lines on Xeon, Itanium Roadmaps

by Timothy Prickett Morgan

The beginning of Intel Developer Forum is always about the big ideas that set the themes for the show and generally chart the course for where Intel wants to take the IT industry (or where Intel think the IT industry is going to take it). Day two is about the giving a little more detail--but just enough to whet the appetite. And last week Mike Fister, general manager of Intel's Enterprise Platforms Group, said just enough about its Xeon and Itanium processor plans for the next two years to make its systems partners hungry without telling them everything that is on the menu. Intel's plans for its Xeon and Itanium lines so impact the Unix market, since the open source FreeBSD and SCO UnixWare and OpenServer all run on 32-bit X86 platforms, and so does Sun Microsystems's Solaris. And Hewlett-Packard, of course, has bet the farm on Itanium with its HP-UX Unix variant.

Only a few weeks ago, Fister had laid out how Intel's long-term plan was to keep the Itanium processors delivering twice the performance as Xeons and getting the cost of the server platforms at parity by 2007. There will be a lot of processors, related chipsets, and chip-making processes announced before that can happen.

Taking it from the bottom up, Fister said that the "Nocona" Xeon DP processors that Intel would deliver in the second quarter--and the first processors to support the new 64-bit memory extensions that we the talk of IDF this week--would run at 3.6 GHz and would have 1 MB of L3 cache memory.

Up until now, Intel had not divulged the feeds and speeds of Nocona, other than to say that the chips would support 400 MHz DDR2 ECC main memory and an 800 MHz front side bus. The Nocona will support the "Lindenhurst" chipset for dual-processor servers and the "Tumwater" variant aimed at high-end workstations; motherboards based on these chipsets will be able to support up to 16 GB of main memory in four slots using 4 GB DIMMs that use considerably less power and generate a lot less heat than machines using 1 GB or 2 GB DDR DIMMs.

The future "Jayhawk" kickers to Nocona will also work in the Lindenhurst and Tumwater chipsets, and are probably Nocona's with larger cache and more features activated that are latent in their cores (like HyperThreading was latent in the prior "Northwood" Pentium 4s and 64-bit was latent in the new "Prescott" Pentium 4s). Further out in 2005, Intel will deliver new chipsets that support the Jayhawks as well as an as-yet unnamed successor to them in the Xeon DP line.

Intel didn't really say much more about the Xeon MP machines this week at IDF. Intel is expected to imminently announce a 3 GHz version of the "Gallatin" Xeon MP with 4 MB of on-chip L3 cache memory, which will plug into existing Gallatin machines. It won't be until early in 2005 that Intel will start shipping the "Potomac" kickers to Gallatin, which will use a beefed up variant of the Lindenhurst chipset called "Twin Castle" that supports DDR2 main memory, 64-bit addressing, and an 800 MHz front side bus.

In the second half of 2005, Intel will roll out a dual-core implementation of Potomac called "Tulsa." It is not yet clear if the Tulsa processor will support HyperThreading as well as chip multithreading. In an interview, Fister hedged and said that Intel was keeping its options open and that in some cases, it might make sense to have both dual-cores and HyperThreading in the same chip.

Fister said that all of the Xeons going forward would support three different modes: 32-bit applications on 32-bit operating systems, a so-called legacy mode; 32-bit applications running in "compatibility mode" on a 64-bit capable operating system; and a full-blown 64-bit mode for applications running on a 64-bit operating system. While he did not get into the nitty gritty of how the 64-bit extensions are implemented, he did say that the new Xeons would have 64-bit pointers and registers, would include 64-bit double precision integer processing, would have eight new SSE registers and eight new general purpose registers, and would support a flat virtual address space.

On the Itanium MP front, Fister said that the updated "Madison" Itanium 2 processor that is expected in the second half of this year would include 9 MB of L3 cache and would run at 1.7 GHz. It will probably provide about 15 percent more performance on workloads that don't care all that much about L3 cache than the current 1.5 GHz Madison chip, but could do a bit better than that on cache sensitive applications.

Fister didn't say much new about the dual-core "Montecito" Itanium due in 2005, which will be built using Intel's 90 nanometer chip making technology and have a gigantic 24 MB L3 cache. Beyond that, the "Tukwila" Itanium chip, which is being designed in conjunction with the engineers Intel picked up from the defunct Alpha processor team from Compaq, will come out in 2006, probably with four cores on a single chip.

The news at this IDF was centered more on the Itanium DP front. The current "Deerfield" Low Voltage Itanium 2 DP processors, which ship in two-way servers aimed primarily at HPC clusters, current run at 1 GHz or 1.4 GHz and have 1.5 MB of L3 cache. Later this year, Intel will launch a new Itanium DP chip dubbed "Fanwood" that will come in the regular DP and the low-voltage DP flavors. The Fanwood DP will run at 1.6 GHz and have 3 MB of L3 cache, while the LV Fanwood DP will slow down slightly to 1.2 GHz and have 3 MB of L3 cache.

In 2005, when the dual-core Montecito Itanium MPs ship, Intel will ship DP and low voltage DP variants of this chip called "Millington," and the Tukwila four-core chip will also have these two DP variants as well, known as "Dimona." Intel has not given out any of the feeds and speeds on these future Itanium DP processors, but wanted mainly to make it clear that it will continue to deliver three different styles of Itanium chips for the foreseeable future.

The Montecito chips will use a new chipset called "Bayshore," which will support DDR2 main memory, PCI Express peripheral interconnects and "faster" front side buses. The Montecito chip will also incorporate a new feature called Pellston Technology (PT) that will improve the reliability of data storage in Montecito's cache memories, and another feature called Foxton Technology (FT), that will allow a Montecito chip that is running cooler than its design specs to automatically go into a burst mode to finish processing work quicker so long as the chip doesn't exceed Intel's and user's thresholds for heat output on the chip. Montecito will also have more sophisticated power management features--essentially Intel is going to play with the voltage to keep it cool when workloads are not demanding--thus lowering the electricity usage and heat profile of the Itanium, which has been one of the limiting factors in its adoption in servers.

In addition to these technologies, Intel is working on a variant of the Vanderpool Technology (VT) feature that it demonstrated this week on desktop systems, which enables partitioning of a single Xeon processor into multiple virtual machines. On the server front, a variant of Vanderpool code-named "Silvervale" will be embedded in the Xeon and Itanium server processors that Fister says will borrow ideas from Vanderpool but will in reality add hardware support for virtualization technologies already created by the likes of VMware, IBM, Hewlett-Packard, Microsoft and others for their server platforms. At this point, it looks like Silvervale technology, or ST, is not fully cooked and will merely facilitate physical and logical partitions.

Exactly how this will be accomplished, Fister would not say in the interview, except to say that it will involve a certain amount of standardization among the various server vendors and their very different ways of doing virtualization and that Intel was working with server makers on how best to do this. Silvervale will be available on both Xeon and Itanium processors. Fister did not say when it might arrive on the scene.

Server Makers Swear Fealty to Intel's Xeon, Itanium Plans

by Timothy Prickett Morgan

Three out of four is a pretty good average in most games, and so it is with Intel and the tier-one server vendors. Last week, at Intel Developer Forum, three of the top four server makers--Hewlett-Packard, Dell, and IBM--all took to the stage and with varying degrees of enthusiasm and lots of marketing speak endorsed both the future 64-bit enabled Xeon and the Itanium components that Intel will deliver over the next two years.

Sun Microsystems was not asked to take the stage with Mike Fister, general manager of Intel's Enterprise Platforms Group, presumably because it is not yet a high volume player in the X86 server market and because it has decided to use Opteron-based systems from Advanced Micro Devices as the basis of a new line of entry and midrange Unix and Linux servers.

Shane Robison, chief technology officer at HP, explained--as he has many times in the past several years--how the company was collapsing a disparate group of enterprise servers using 64-bit Alpha, PA-RISC, and MIPS processors to the Itanium line and will continue to push Pentium-based ProLiant servers, too.

HP executives representing both the Integrity and ProLiant lines said later at the show that the company was obviously pleased that 64-bit extensions would allow certain customers using two-way, four-way, and eight-way servers to worry less about memory use than has been possible in a restrictive 32-bit architecture.

Don Jenkins, vice president of marketing for HP's Business Critical Systems unit explained that because of the 32-bit memory limits, plenty of 32-bit applications running out there in the world have been tweaked to use processor cycles to compress data and shift pointers to boost the performance of those applications. With real 64-bit support and more registers, 32-bit applications can be tweaked to stop doing this and therefore gain back some CPU cycles that were lost doing memory tricks and also be able to handle larger data sets than was possible. Any new Windows or Linux applications that developers create will not have to worry about this, particularly since the Xeons will support a single 64-bit virtual address space, not the paged memory architecture of the 32-bit Xeons, which is itself a legacy of the 16-bit X86 era.

Susan Whitney, general manager of IBM's xSeries Intel-based server line, said Big Blue was excited by the 64-bit extensions and the company would be delivering extended Xeon blade servers for its BladeCenter machines as well as putting the new chips in its xSeries tower and rack servers.

With its eight-way and larger server business raking in the bucks, IBM is perhaps more relieved at the larger main memories than even HP when it comes to the Xeon line. IBM's Summit-II xSeries 445 servers support 16-way configurations today and will soon support 32-way processing. IBM is expected to go to 64-way processing sometime later this year. The only reasonable way IBM can deliver 32-way and 64-way Xeon-based servers is by having 64-bit main memory. With a 32-bit machine, there is a 64 GB upper limit on the size of shared main memory, no matter how many processors are in the box. A 32-way machine with only 64 GB of main memory is not balanced, and there is no way a 64-way machine with only 64 GB of main memory will work properly running the kinds of big applications and databases that IBM likes to sell top-end xSeries to support.

Whitney was careful, of course, to say the Itanium processor would still have a place at IBM and that its Summit chipsets had been engineered to support both Xeon and Itanium processors. Whether IBM pushes Itanium servers as hard as it might have otherwise had the 64-bit extensions not appeared in the upcoming Xeon, Xeon DP and Xeon MP server processors is a subject of debate. But from IBM's perspective, now the reach of Xeon has clearly been extended.

The people at Dell, which is aspiring to be the volume leader in the X86 server market and which still makes most of its shipments and money peddling uniprocessor and two-way servers, are very happy about the 64-bit support in the future Xeons and are, as has been the case for years, lukewarm when it comes to endorsing Itanium, and certainly do not want anything to do with Unix. For Dell, Linux is its Unix.

Kevin Kettler, chief technology officer at Dell, took the stage with Fister and had written his talking points on his fingers in ink, and it was significant, in a classicly Freudian way, that he wrote a reminder on his pinky to talk about Itanium as his last point--the last and smallest finger.

Dell was one of the early vendors to ship a four-way server using the first generation Merced Itanium processors, which were, to put it bluntly, a dud. Dell now sells a two-way Itanium 2 PowerEdge server that it peddles mostly in the high performance computing (HPC) market, where the kind of superior floating point performance that Itanium delivers compared to Xeon is more important than low cost, low power consumption, or compactness.

If scalability of SMP systems is a measure, then Itanium is clearly not as important to Dell as it is to either HP, which has two-way to 64-way Itanium machines, or IBM, which has two-way to 16-way machines. Kettler said there has been a lot of customer interest in the 64-bit extensions to Xeon, and the company is expected to stay consistent in its message that it is best to build large, flexible infrastructure to support Web, application, and databases by clustering two-way and four-way servers.

It is hard to say for sure, in the end, exactly what impact the 64-bit extensions for Xeon will actually have on the servers these vendors make and promote and the ones that customers buy. And none of these vendors--and indeed, the others like Fujitsu-Siemens, Unisys, and perhaps even Sun who will follow suit by announcing support for the 64-bit Xeons--will have much of an idea of what the impact of 64-bit Xeons will be until the Nocona two-way and Potomac four-way and larger processors get into systems and the operating systems and applications that run on them have been tweaked to support those extensions. It will be well into 2005 before all of this happens.

AMD Keeps the Heat on Intel with Low-Power Opterons

by Timothy Prickett Morgan

Advanced Micro Devices announced last week that it was extending its 64-bit Opteron workstation and server chips with two new low-power variants. The Opteron HE processors consume around 55 watts of power and the Opteron EE processors consume about 30 watts of power. While this does not allow these chips to be used in fanless environments, this does make them appropriate in places where Intel Corp is currently deploying its "Prestonia" Xeon DP processors, mainly in workstations, blade servers, and small form factor rack-mounted servers.

The Opteron HE and Opteron SE processors will be available in the middle of March, and the company says that they will offer the most oomph per watt in the X86 market. The Opteron 846 HE (2 GHz) and 840 EE (1.4 GHz) processors will sell for $1,514 each for 1,000-unit quantities. The Opteron 246 HE (2 GHz) and 240 EE (1.4 GHz) chips will cost $851 each in 1,000-unit quantities, while the Opteron 146 HE (2 GHz) and 140 EE (1.4 GHz) will cost $733 each for 1,000 units. As we go to press, AMD has still not explained how it has been able to lower the power consumption and heat dissipation of the new Opteron HE and EE chips, but it has probably either moved to a 90 nanometer fabrication process from the current 130 nanometer process used for the initial Opterons, cut out some of the cache memory for the chips, or done both at the same time for the lowest power profile versions.

These prices are at premium compared to the previous Opterons with the same numerical designations and clock speeds, which also had their prices slashed by between 7 and 51 percent this week as AMD tries to keep the heat on Intel in the battle for the hearts and minds of the server market.