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U.S. Commits to Building World's Fastest Supercomputer

Rather than pick any one architecture, Oak Ridge is going to rely on a mix of architectures to create this behemoth, which will complicate the task of deciding whether the cluster is the most powerful supercomputer in the world. That said, the deal is a big win for rebounding vector supercomputer maker Cray. Oak Ridge will be expanding its Cray X1 parallel vector super to 20 teraflops this year and will add a 20 teraflops "Red Storm" Opteron-Linux supercluster in 2005. The Argonne National Laboratory, which is networked to Oak Ridge, will be installing a 5 teraflops Blue Gene/L Linux supercomputer (IBM's third commercial Blue Gene sale). In 2006, Oak Ridge will add a 100 teraflops Cray X2, the kicker to the X1, which will be upgraded to a 250 teraflops machine by 2007. Silicon Graphics apparently has been awarded some DOE contracts for the Oak Ridge upgrade, but the details were not available at press time.

The massively parallel vector supercomputer known as Earth Simulator, built by NEC for the Japanese government, is the current top-end supercomputer in the world, with 40.9 teraflops of peak performance and an impressive 35.9 teraflops of sustained performance. The 252 processor Cray X1 at Oak Ridge is rated at a mere 2.9 teraflops of sustained performance and 3.2 teraflops of peak performance. Both the NEC and the Cray designs, unlike many clusters, use vector processors and are very efficient at what they do. On many Unix and Linux superclusters, 60 percent of the aggregate computing capacity goes up the chimney.

General Motors Buys 9 Teraflops IBM Unix Super

Intel Server Chip General Manager Moves to CEO Post At Cadence

Designing sophisticated electronic components and getting them to market successfully is a tricky business, and very few people in the world probably know this as well as Mike Fister, former general manager of Intel's Enterprise Platforms Group. Fister knows the challenges that chip makers, both large and small, face as they try to innovate with new technologies, which is why Cadence Design Systems, one of the big players in the electronic design automation (EDA) software area, has tapped Fister to become its new CEO and president.

As a senior vice president and general manager at Intel, Fister had a fair amount of control over the server, workstation, chipsets, and related technologies that drive a fair portion of Intel's $30 billion in annual sales (exactly how much, Intel will not say) and arguably a very large portion of its billions in profits. Fister, who is 50, spent 17 years at Intel and was responsible for bringing the later generations of Intel's 80486 processors (the ones without the bugs) to market, as well as bringing the Pentium Pro, Pentium II, Pentium III, Celeron, Pentium II Xeon and Pentium III Xeon chips to market. He has also been one of the champions of the 10-year, 64-bit Itanium line of chips codesigned by Intel and server maker Hewlett-Packard and, of late, has been the person who has explained why Itanium is better than Opteron and then reversed that position to launch the Xeon with 64-bit extensions, in February. As a self-proclaimed gear head, the Intel job was a lot of fun, but Itanium has been something of a bummer until recently, when performance finally got on par with RISC/Unix processors. Because of his close association with the Xeon and Itanium roadmaps, which have been radically changed a number of times in the past year, there will be plenty of talk about whether Fister left or was asked to leave. Officially, Intel says that Fister is resigning.

The jump to Cadence is an unexpected but logical one. The company has 4,800 employees and is a $1.1 billion provider of software and services to many of the largest and smallest chip makers in the world and one of the big players in a $4 billion industry. With Paul Otellini tapped to be president and chief operating officer at Intel last year and presumably the next CEO at the company, when Craig Barrett retires next spring, Fister's upward mobility was probably limited. By moving to Cadence, he becomes CEO and president in charge of one of the companies that Intel will tap to try to give it the tools to create all of the new sophisticated processors it needs to make to stay in the market. Fister, as one of the guys most frustrated by the limitations of current EDA tools to speed up design, ferret out flaws and bugs, and improve yields, is the best person to sell Cadence tools into Intel.

This is an obvious reason why Cadence wants to hire way one of the top guns at what could turn out to be its largest customers. But, according Ray Bingham, current CEO at Cadence, who is ascending to the chairman role, the company wanted Fister as its top executive because he is the one who forged all of the partnerships with workstation and server markers that drove Intel's share of those markets ridiculously high during the past decade.

The role of CEO is not necessarily going to be easy at Cadence, however. The big chip makers play the EDA software makers against one another to drive down the cost of the software, and a key metric for the semiconductor business--ASIC design starts--is decreasing. However, Cadence has some advantages and plans to attack new markets and new geographies to build its business. The company touted its open framework and database software, which makes it easier for companies to deploy, use, and integrate with other tools. Fister, who is on his first day on the job, called the shot just as he would have at Intel. "You just have to be confident that you can set a standard and then go ahead and execute," he said in a call with Wall Street analysts and reporters yesterday. "People will pay--and pay differentially--if they can offset some of the human cost and potential waste as they drive efficiencies, because this affects their profitability."

Bingham and Fister explained that Cadence planned to "identify adjacencies" to their core EDA software that directly affect yields and then try to gain new business; they also suggested that the company might work from the chip out to higher and higher abstraction levels to encompass complete systems. Finally, as chip making moves ever into new markets where environmental laws are arguably less stringent than in the United States and Europe and labor is cheaper, Cadence will pursue business with chip upstarts. Many of these companies will inevitably compete with Intel, as well as with other Cadence partners, such as IBM, Fujitsu, HP, and Agilent.

Over at Intel, Abhijit Talwalkar, who was vice president of the company's Enterprise Platforms Group and general manager of its Platform Products Group, which means he reported to Fister and was responsible for the development of chips, chipsets, and other features of workstations and servers, is taking over Fister's job as general manager of the whole enterprise enchilada. Talwalkar joined Intel in 1993 and has worked at the former Sequent Computer Systems (now part of IBM) and Lattice Semiconductor. Intel also announced that it has broken its Software Solutions Group away from the Enterprise Platforms Group and that comanagers Richard Wirt and Will Swope now report directly to Otellini.

Intel Moves Up Dual-Core Xeons to Blunt Opteron Attack

The IT industry is a volatile one, and you have to be flexible to survive, even if that means throwing millions of dollars into research and development. Chip juggernaut Intel confirmed last week that it is killing off the next generation of its single-core Xeon DP processors for workstations and servers, and its similar processors for desktops, so the company can move more quickly to adopt dual-core products. The move with the Xeon DP and Pentium 4 processors mirrors that which Intel already made with its Itanium processors.

On the server front, the 64-bit "Jayhawk" Xeon DP is now gone from the Intel roadmap. Jayhawk is the kicker to the forthcoming "Nocona" Xeon DP, which is the first 64-bit-capable chip that Intel will roll out with the Pentium 4 core, rather than with the very different Itanium core. As we explained in February, the Nocona chips are expected to ship before the end of June. The Noconas have the new Prescott cores, while the current "Prestonia" Xeon DPs have the older "Northwood" Pentium 4 cores. The Nocona chip will run at 3.2 GHz, will have 1 MB of L3 cache, and will sport an 800 MHz frontside bus. Nocona will be implemented in a 90 nanometer process, just like the Prescotts. The Jayhawk kicker to Nocona was expected in late 2004 or early 2005 and was essentially the same chip but with a higher clock speed and possibly a larger L3 cache. Intel has come to the shocking realization that higher clock speeds are not yielding higher performance, but are creating a lot of heat and burning up a lot of electricity.

With all the RISC/Unix players now shipping dual-core chips, and Advanced Micro Devices widely expected to start shipping dual-core Opterons with the future SledgeHammer-III processors, due in the second half of 2005 (see "Opteron Learning to Walk, Ready to Run" for details), Intel has to do something dramatic to retake the lead and the technical high-ground from AMD. Killing off Jayhawk and its equivalent Pentium 4 desktop processor, "Tejas," and moving its dual-core Xeon program forward is the best way to do that. Intel has not supplied the code names and schedules for these future dual-core Xeons and Pentiums.

As far as anyone knows, the high-end "Potomac" Xeon MP chips, kickers to the current "Gallatin" Xeon MPs that are aimed at four-way and larger machines, are still slated to appear in early 2005, with a dual-core variant of that chip called "Tulsa" due in mid-2005. Whatever the Xeon DP kicker is called, it will probably be a trimmed-down version of the Tulsa chip. But it could use a different core entirely, perhaps based on the Pentium M core for laptop processors. Intel is not, as yet, saying. All of these chips will have the Xeon-64 memory extensions and will support both 32-bit and 64-bit processing. If Intel has something really interesting up its sleeve--four Pentium M cores on a chip with Xeon multiprocessing extensions is rumored--even Tulsa's days might be numbered.

In the past, Intel would have concentrated on ramping up the clock speed to 4 GHz and then 5 GHz, as it moves from 130 nanometer to 90 nanometer to 65 nanometer processes over the next two years. But the Pentium 4 architecture does not scale well with clock speed. Opteron, to put it bluntly, does a much better job, and often delivers the same performance for a lot less clocks and a lot less electricity. By going dual-core, Intel can keep the clock speeds relatively low and still nearly double the performance of a chip. It may even be able to increase performance and step down clock speeds, making the Xeons more competitive. But, of course, AMD is going to do the same thing, if everyone else is right. Intel is in a tough spot, it seems. But cranking up Jayhawk to 5 GHz is not the answer, since that might require vendors to radically revamp the cooling and internal layout of their machines, and still will not provide a substantial performance boost.

1.6 GHz Itaniums Start Shipping

Intel said this week that it has started shipping the new 1.6 GHz, 3MB cache Itanium DP processor, which it announced a month ago for two-way machines. This chip, like the 1.4 GHz, 3 MB cache part announced at the same time, is made using a 130 nanometer process. The 1.6 GHz chip dissipates 112 watts of heat as it runs, a little bit less than the 130 watts that the 1.5 GHz, 6 MB Itanium MP processor dissipates. The 1.6 GHz Itanium DP chip costs $2,408, considerably less than the $4,227 that Intel is charging for the 1.5 GHz Itanium MP part. All of the Itanium processors support the 64-bit implementations of the HP-UX and FreeBSD variants of Unix, as well as various Linux implementations and Windows.

AMD Takes a Chainsaw to Opteron Prices

X86 chip maker Advanced Micro Devices announced new low-power variants of its "ClawHammer" Athlon 64 processors last Thursday, which is interesting news for laptop buyers. But the real interesting news is that, on the same day, AMD cut prices on its 64-bit Opteron X86 server processors by anywhere from 19 to 43 percent.

The price cuts were deepest on its entry Opteron 14X processors, with prices cut to $417 in 1,000-unit quantities, down 43 percent from their former price tag of $733. Prices on the Opteron 24X family ranged from $209 for the Opteron 242 (the least expensive Opteron and the one aimed right at the Intel Xeon DP) to $690 for the Opteron 248, 246 HE, and 240 EE processors. (The HE is a low power Opteron, and the EE is an ultra-low-powered Opteron.) Prices on the high-end Opteron 84X family were cut by 20 to 23 percent, with prices ranging from $698 to $1,165 after the cuts. The Model 84X processors are used in four-way and eight-way machines, which are only now starting to be sold in any appreciable volumes.