Intel Cranks Up the Clocks on Madison Itaniums

by Timothy Prickett Morgan

Chip maker Intel this week announced a tweaked version of its "Madison" generation of Itanium 2 processors that sport higher clock speeds and a faster front side bus. Provided that Intel gets its dual-core "Montecito" Itanium processors out the door at the end of the year and into systems by early next year, as the current plan is, this should be the last iteration of the Madison chips to come to market.

The new Madison Itanium 2 chips come in two flavors. One runs at 1.66 GHz and has 9 MB of L3 cache memory on chip, while the other runs at 1.66 GHz and offers 6 MB of L3 cache. The announcement fulfills a rumor from last fall, prior to when the 1.6 GHz/ 9 MB cache Madison chips debuted, that suggested Intel would ship a Madison processor with a faster front side bus. And indeed, these two Madison processors have a 667 MHz front side bus, compared to the 400 MHz front side bus that has been used by all prior generations of Itanium processors. This chip is an Itanium MP processor, by the way, which means it can only be used in four-way server cell boards. The Itanium DP processors for dual-processor boards run at 1.4 GHz or 1.6 GHz and have either 1.5 MB or 3 MB of L3 cache.

While that extra smidgen of clock speed on the new Madison-class Itanium MP chips will help boost performance a little, that faster front side bus is going to mean a lot more for performance on certain kinds of memory-intensive workloads. Boosting the clock speed on the front side bus, which links the processor to the motherboard chipset and to main memory, means jacking up the bus bandwidth from 6.4 gigabits/sec to 10.6 gigabits/sec. The higher bandwidth means that there is a better chance that data stored in memory can be moved into the processor or into the L1, L2, or L3 caches before it is needed by the processor, which increases system performance. Boosting the bus speed is particularly useful for supercomputer clusters and big SMP boxes that are used to make such machines.

These improved Madison processors are laying the groundwork for the forthcoming Montecito Itaniums, which will plug into machines using the same chipsets and taking advantage of the same higher front side bus speed.

The new Madison chips are built using the same 130 nanometer process used to create other Itanium chips, and the relatively poor yields on that process are the main reason why the Madison 9 MB chips came out at 1.6 GHz last November instead of the 1.7 GHz, 1.8 GHz, and 1.9 GHz clock speeds that were expected. The thermal envelope inside the servers is another issue. That larger 9 MB cache is great to boost performance, but it is also hot. At 1.6 GHz, the Madison 9 MB chip consumes about 130 watts of juice, and it would be considerably higher at 1.9 GHz. Intel and its server partners have topped out the thermal window for Itanium MPs at 130 watts per chip because to go any higher would cause them to do a substantial redesign of their motherboards and chassis. Given the relatively low volume of Itanium shipments, it is just not worth the trouble to revamp the servers using Madisons--especially when dual-core Montecito chips using a 90 nanometer process and packing 24 MB of L3 cache are right around the corner, will plug into the same chip sockets, and will probably have a 100-watt thermal envelope at the same 1.6 GHz and maybe 130 watts running above 2 GHz.

Intel singled out Hitachi, its latest partner on the Itanium front, for an honorable mention in the latest Madison announcements. Hitachi has created a blade server called the BladeSymphony that uses the new Madison chips with the 667 MHz front side bus and its own chipset. The BladeSymphony server is an eight-socket blade with 256 GB of main memory that Hitachi expects to launch as the core of a clustered Linux server within the next month. The BladeSymphony is interesting in that it is breaking a few rules. The blades have two processors per blade, which should mean that Hitachi is using the Itanium DP chips. But Hitachi is allowing customers to use fiber optic interconnections and special SMP electronics to link up to four blades together into an eight-way SMP server. That is presumably the symphony part of the box. Hitachi will also offer 64-bit Xeon chips on the BladeSymphony blades, which can be intermixed in a chassis (which holds up to eight blades in a 10U form fact). However, Xeon and Itanium blades cannot be linked into an SMP cluster.

The 1.66 GHz/ 9 MB Madison with the 667 MHz front side bus costs $4,655 in 1,000-unit quantities, and the 1.66 GHz/6 MB Madison with the 667 MHz bus costs $2,194. With a 400 MHz bus, the Madison Itaniums sell for $4,227 and $1,980, respectively. So that tiny bit of clock performance and that 65 percent improvement in bus speed translates into a 10 or 11 percent premium on the price.

The question that server buyers have to ask themselves is this: For their workloads, will a 3.3 GHz/8 MB "Potomac" Xeon MP, which is also a 64-bit processor and which also has a 667 MHz front side bus, deliver about the same performance on their workloads as the new Itaniums? That chip costs $3,692, which is 21 percent cheaper than the Itanium chip. Here's another question: If you drop down to the 3 GHz Potomac with 8 MB L3 cache, the price falls to down to $1,980 for the chip, which is 57 percent less expensive for what could be about the same performance. For many workloads, the new top-end Madison and the penultimate Potomac will offer indistinguishable performance, but the Itanium chip is bigger, hotter, and considerably more pricey. The main benefit of the Itanium chip is that it is being offered in flagship enterprise servers from Hewlett-Packard, Unisys, NEC, Fujitsu-Siemens, and soon Hitachi.