Sun Polishes Up Sparc T2 Multithreaded Chips

Published: August 9, 2007

by Timothy Prickett Morgan

A cynic might suggest that Sun Microsystems broke its Microelectronics chip division free of its Systems group in late March just so it could get twice as many Sparc-related press releases to market. Otherwise, Sun would not be launching the "Niagara-2" Sparc T2 chip this week as a separate product, but would have to wait until its next generation of servers was ready for market some time before the end of this year and then talk about the chip as a component of the overall machine.

But because Microelectronics is again its own division, as it was in days gone by at Sun when the company dreamed of licensing its Sparc RISC designs to lots of companies and creating a humongous Sparc ecosystem, and because Sun needs to keep Wall Street focused on the good technology it is creating, the Niagara-2 chips got their own coming out party in Santa Clara on Tuesday.

The original Niagara Sparc T1 chips made their debut in December 2005 in single-socket T1000 and T2000 servers, which came in 1U and 2U server form factors. The designs for these chips as well as the documentation and hypervisor microcode for the chips were released under the GNU General Public License 2 license a few months later and became the foundation for the OpenSparc project. The Niagara-1 chips had eight processor cores, each with four instruction threads, plus four integrated memory controllers, a JBus interface, and a PCI Express interface all integrated into the design. The original Sparc T1 chips had a top-speed of 1.2 GHz and had a thermal design point (TDP) or 72 watts running normal workloads and 79 watts under peak loading. This Niagara-1 chip has around 300 million transistors, a 379 square millimeter die size, and was implemented in a 90 nanometer process created by Sun's chip fabrication partner, Texas Instruments. (Sun has never made chips, but rather only designs them for manufacturing by others.) Sun put out T1 chips with anywhere from two to eight cores active with clock speeds of 1 GHz or 1.2 GHz; in January 2007, it cranked up the clocks to 1.4 GHz on some T1 parts.

Back in February, at the annual IEEE's International Solid State Circuits Conference in Silicon Gulch, Sun presented a paper on the Niagara-2 chip and had talked to analysts about a two-socket variant of the Sparc T series design called "Victoria Falls." Here's what Sun said back then about the T2 chip: it has eight cores, each with eight threads and each with a floating point unit. (The Sparc T1 chips have a single floating point unit for the entire chip.) The Niagara-2 chip has 4 MB of L2 cache, one x8 PCI-Express slot, two 10 Gigabit Ethernet ports (which are a variant of the "Project Neptune" 10 GE chip that Sun has designed for its own use and hopes to license to other network equipment providers), and 8 FB-DIMM memory slots driven by an on-chip memory controller. The Niagara-2 chip has 500 million transistors and a 342 square millimeter die size; it is implemented in an 11-layer, 65 nanometer process from TI. The Sparc T2 can only be used in single-socket servers, just like the Sparc T1 chip.

The news this week, according to Rick Hetherington, chief technology officer at the Microelectronics division at Sun, is that the T2 chips will not plug into the same sockets as the T1 chips. Sun is also divulging that the T2 processors will come in 900 MHz, 1.2 GHz, and 1.4 GHz clock speeds initially, and if the 65 nanometer process allows for it, Sun will crank up the clock speeds as chip vendors always try to.

But Sun has thermals to contend with, too, and that means it has some limits. With 500 million transistors in the T2 design--a lot of which comes from the integrated 10 GE networking--Sun wants to keep the electricity usage and heat dissipation down. With six cores running (that's 48 threads) at 900 MHz, the T2 chip will burn at about 60 watts, which is pretty impressive considering all of the stuff that is integrated on the chip. But with all eight cores activated and running an intense workload like SPECfp_rate, the T2 chip running at 1.4 GHz hit a high of 123 watts. Hetherington said that with a typical workload, like a Java stack, running on it, the fully activated T2 chip should consume about 100 watts, maybe a little bit more. Sun is only expected to launch machines using the 1.2 GHz or 1.4 GHz parts with four, six, or eight cores activated. The slower, cooler 900 MHz part is apparently experimental at this point, but could end up in blade servers if customers with heat issues ask for it.

Part of the reason why the T1 and T2 chips perform so well is that their design focuses on increasing memory bandwidth and keeping processor clock speed as low as possible while increasing the number of threads. The original T1 design could keep its 32 threads busy about 75 percent of the time, and it will be interesting to see how well the T2 does in this regard. The T2 has an immense aggregate memory bandwidth that is north of 60 GB/sec, so it stands to reason that Sun has created the T2 to keep those cores and threads busy.

The T1 chip had 1,111 pins and its socket was considerably larger than the T2 chip, which has only 720 pins. Moreover, of the 720 pins, 200 of these are used for testing the chip as it runs, so Sun's new I/O design with the T2 chip is a lot more streamlined than with the T1. All of the links between I/O, networking, and memory are serial links, rather than the parallel links used in some parts of the T1 chip. This is what contributes to higher bandwidth between components, and it is also laying the groundwork for multi-socket Victoria Falls Sparc kickers, which are due in Sun's systems sometime in the first half of 2008.

Sun is not saying much about performance when it comes to the T2 chips, but the T2 is expected to have about 2.5 times the throughput performance of the T1, and Victoria Falls is expected to nearly double that again, with a 65 percent performance boost over the T2's at the system level.

As it did with the T1 designs, Sun is expected to open source a significant part of the T2 design, and Hetherington said that Sun would once again use the GPL v2 license for this, not the new GPL v3 license that has just been drafted. The OpenSparc T1 specs and code were downloaded 5,400 times, which is a lot considering the very specific nature of chip designs. (It is not like software, which you can compile and run anywhere. Relatively few people or companies have the funds to tweak a chip design and then fab it.) Sun is hoping to release the intellectual property behind the T2 chip by the summer of 2008; it is unclear why this takes so long. Sun is, however, launching an OpenSparc T2 beta review program to give customers and partners early access to the T2 designs.

Sun is being vague about when its T2-based servers will come to market, but you can bet it is trying to get them out the door as fast as it can.

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