Intel's Nehalems to Star at IDF, AMD Pitches Shanghai

Published: August 21, 2008

by Timothy Prickett Morgan

The ongoing saga of Intel and Advanced Micro Devices goes on this week, as Intel will be hosting its semi-annual Developer Forum in San Francisco and will, among many other things, be showing off its impending "Nehalem" upgrade to the current "Penryn" family of Core processors. The Nehalem chips, slated for later this year, will be Intel's first true quad-core processor and will sport a new processor socket an interconnection mechanism called QuickPath Interconnect.

In essence, the Nehalem chips will be architectural cousins to AMD's own Opteron processors and their HyperTransport interconnect. And as you might imagine, given AMD's bug in the "Barcelona" quad core Opterons a year ago, which gave Intel the pole position in the X64 server market again after several years of AMD leading in the technology arms race, this kinda burns AMD's top brass a bit--those that haven't left or been fired in recent months, anyway. (And maybe those that have left, too.) But, that is the burden of being right. Being right is never sufficient; you have to execute on the ideas that make you right, too. AMD did this with the original "Hammer" family of Opterons and also with their dual-core successors, but lost ground in the jump from two-core to four-core chips while at the same time lagging Intel in chip making process technology. That latter bit left Intel open to crank up its chip fabs, shrink its chips, and cram lots of cores into a socket--even if Intel did so with less elegance with its quasi dual-core and quad-core designs. None of that mattered when Intel could put chips that looked and smelled like dual-core and quad-core processors (at least as far as CIOs and operating systems knew) into the field and AMD was lagging.

Last week, as the IT press was getting ready to cover Intel's announcements, AMD hosted a teleconference to talk about integrated graphics performance--something Intel is expected to talk more about at IDF as it details its plans for graphics chips in general and its "Larrabee" project in particular--and provide a little more guidance on when its future "Shanghai" quad-core processors, which are a 45 nanometer shrink of the tweaked Barcelona chips, themselves implemented in a 65 nanometer process. As we reported back in May when AMD totally revised its chip roadmaps, the Shanghai chips will have 6 MB of shared L3 cache (more than three times that of the Barcelonas) and 512 MB of L2 cache per core (double that of the Barcelonas). The AMD-V hardware-assisted virtualization features in the Opterons are also being improved to allow for 25 percent faster virtual machine migrations inside a system.

The Shanghai chips will support 800 MHz DDR2 main memory as well, which runs about 10 percent faster than the 667 MHz DDR2 main memory used with the Barcelonas. The Shanghai chips will also include support for the HT-3 HyperTransport interconnect, and will plug into the existing Socket F1 CPU sockets (formerly known as the Rev F socket or the Socket 1027). nVidia nForce 3050 and 3600 chipsets and Broadcom HT-1000 and HT-2100 chipsets will therefore support the Shanghai chips, just as they supported the dual-core "Santa Rosa" and quad-core Barcelona Rev F chips. The Shanghai processors are expected to be available in standard, Special Edition (SE for short, and meaning higher clock speed and much hotter temperature), and Highly Efficient (HE, and meaning lower voltage and therefore lower heat for a given clock speed) variants.

There isn't a lot of news on the Shanghai front, but Randy Allen, general manager of AMD's Computing Solutions Group (formerly its server and workstation division), said on the call that AMD's execution "has been really stellar in the early part of 2008" and that AMD was "delighted with our progress and we have our swagger back." Allen also accused Intel of "photocopying" AMD's innovations--which is basically true, you have to admit--and then asked the IT press to lean on Intel to find out when Nehalem processors would make their way into two-socket and four-socket servers. (The answer is: not as soon as Nehalem makes it into desktops and entry single-socket servers.)

With AMD expecting to have the 45 nanometer process and the Shanghai chips out the door "later in the year" and Intel possibly not having Nehalem chips ready in the key server markets that are being driven by virtualization efforts these days--big boxes are in again in a lot of data centers--Allen wanted to give everyone the impression that Shanghai can and will compete against the Penryn Xeon processors that Intel will have in the field, with their old front side buses and large caches. Allen was not happy about everyone wanting to nail down a ship date for Shanghai chips, but after lots of pressing he said he expected AMD to deliver the chips early enough in the fourth quarter of this year that its server partners can get machines into the field before the end of 2008. Allen said that production wafers are started in the labs, and that AMD is on or ahead of schedule for Shanghai in terms of timing, clock speeds, and yields. He added that in the first half of 2009, AMD will roll out HyperTransport 3 interconnect, PCI Express-2 peripheral support, and new virtualization capabilities for the Shanghai family of Opteron platforms. Allen had no comment on the combined CPU and GPU efforts underway at AMD, and was not in a position to talk about the "Smart Asset" effort being headed by chairman Hector Ruiz to streamline AMD's manufacturing processes or possibly to sell off AMD's chip plants and go fabless.

As we go to press, Intel has not yet briefed the IT community on its Nehalem plans, but in the run up to IDF it did say that the Nehalem chips for the desktop would retain the Core product brand with the addition of the tag "i7" to the name. Heaven only knows what the i7 means.

That said, there is plenty of chatter out there about what Nehalem will look like. The chips will come with two, four, or eight cores on a single piece of silicon, which will allow Intel to dial frequencies up on devices with few cores and go for throughput on devices with many cores. (You can go after two different types of workloads that way, with the quad-core being the middle of the road.) As we all know, the Nehalems will be implemented in a 45 nanometer process that Intel rolled out with the Penryn Xeons in the fall of 2007. The Nehalems will have an on-chip memory controller for DDR3 main memory and for desktop and laptop variants, it will have a graphics processor integrated into the chip package but not on the same die as the CPUs. Each Nehalem chip is expected to have 32 KB of L1 instruction cache, 32 KB of L1 data cache, and 256 KB of L2 cache; up to 3 MB of shared L3 cache will also be on the Nehalem for the cores to play with. Intel is expected to hammer on the concept that, chip for chip, a Nehalem will offer 10 percent to 25 percent more performance than a Penryn chip in the same thermals for single-threaded applications, and the eight-core version will be able to offer about twice the oomph as a quad-core Penryn on thread-friendly workloads at the same power draw. The two-socket variant of Nehalem for servers is code-named "Beckton," apparently, with "Gainestown" being the four-socket version. There's some talk that the 2P boxes will only support four cores, while the 4P boxes will get eight cores.

We'll all let you in on whatever details Intel provides in next week's issue.

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