Sun Talks Up Niagara-2 Sparcs, Begins Work on Niagara-3

Published: October 26, 2006

by Timothy Prickett Morgan

Server maker Sun Microsystems might be gung-ho for Advanced Micro Devices' Opteron X64 processors, but it still believes that it can offer differentiation and value in its own Sparc processor line. Which is why the company is beginning work on the third generation of its "Niagara" Sparc T1 multicore processors and is putting the finishing touches on the second generation of these processors.

Sun has been briefing its peers in the computer industry as well as its customers on what the future Niagara-2 chip, which will very likely be called the Sparc T2 when it is commercialized, might look like, and has confirmed that it is working on yet another future generation of these processors. One of the reasons why Sun can commit to the substantial investment in Sparc processor and related system development is because of the success of the Sparc T1000 and T2000 servers. These machines are selling at a run rate of about $400 million a year right now, can support Sparc/Solaris applications (meaning they do not require a port to the X64 architecture), and can stand toe-to-toe with entry X64 servers in terms of price, performance, and thermals. Moreover, Sun has gotten a lot more press for the T1 chips and their related systems than it has for its other Sparc products, mainly because they show where Sun is either leading or holding steady with server alternatives in terms of engineering, performance, and thermals.

Perhaps Sun should have saved the T2000 name for the Niagara-2 line of servers and called the machines that use the T1 chips the T1100 and T1200, respectively, with the second number being for the rack size in standard units. If you are a conspiracy theorist, the fact that Sun did not make the names of the servers somehow relate to the chip generations might suggest that Sun was not sure how the Niagara machines would do and that its commitment was not all that firm out into the future. But it seems safe to say that now that Sun has stabilized its financials, has rejiggered its management team, and is embracing open source technologies as well as fostering them, the Niagara chips have as safe a future as any chip can have in this rough-and-tumble server market.

To keep interest high in what it is doing with the Niagara chips, Sun has been releasing some of the details on its future Sparc T1 processors to customers and other interested parties in the chip business, such as competitors. Thanks to the kindness of strangers, I have been able to get my hands on such a presentation for the Niagara-2 chips. And the presentation clears up some of the mystery around this future chip, which should appear in T1000 and T2000 kickers sometime in the second half of 2007. (Officially, Sun said "mid-to-late 2007.")

The Niagara-1 chip has eight simplified Sparc cores that are capable of supporting four instruction threads each, and it runs at 1 GHz or 1.2 GHz. It is implemented in a 90 nanometer process and is manufactured by Texas Instruments. The Niagara-1 chip includes 3 MB of L2 cache, shared by all the cores, a DDR2 main memory controller, a PCI Express I/O controller, a JBus interconnection port, and a cryptographic accelerator.

Depending on the applications, the thread scheduler is able to get the threads to run at about 75 percent efficiency, which is truly remarkable. And that means that a 70 watt to 75 watt Niagara-1 chip can do about the same amount of Web infrastructure or database processing work as a single dual-core Xeon or Opteron processor with a much higher clock speed and significantly higher electricity usage and heat dissipation. When Niagara was being designed, Intel's Xeon chips were much hotter than the new Core architecture designs are today, so Niagara was looking very impressive before it launched compared to X64 chips, but AMD and Intel caught up on some fronts.

As Sun has already said many times, Niagara-2, which taped out in April of this year, will be built using a 65 nanometer process. By moving to skinnier circuits, Sun can pack more stuff on the Niagara chip, crank up the clock speed, or do a little of both.

According to the documents I have from Sun, the company's goal is to double the amount of throughput in the Niagara chip with the Niagara-2, and the company will accomplish this, in part, by doubling the number of threads in each core from four to eight. Sun is also working to improve the single-thread performance with the Niagara-2 and integrate more networking and cryptography features.

The Niagara-2 chip will have eight cores, and it is expected to run at around 1.4 GHz. The chip has a bigger L2 cache at 4 MB, which is set up on the chip in eight banks, and has a 16 KB L1 instruction cache and 8 KB of L1 data cache. The chip will also have four dual-channel FBDIMM memory controllers that run at 667 MHz implemented in silicon, which means Sun is moving away from the DDR2 main memory used in the Niagara-1 and now the Rev F Opterons. The chip also includes two 10 Gigabit Ethernet ports that have packet classification and filtering functions built into the circuits; these ports will also support legacy Gigabit Ethernet links. Niagara-2 also has one PCI-E x8 I/O port implemented in silicon.

Perhaps most significantly, the Niagara-2 chip will have a floating point/graphics unit, the absence of which has kept the Niagara-1 chip from being deployed in some commercial and scientific settings. The integrated cryptographic processor on Niagara-2 supports RC4, DES/3DES, AES encryption (128, 192, and 256 bit for the latter) as well as the MD5, SHA-1, and SHA-256 hashes; significantly, the cryptographic processor is designed so it can feed two 10 Gigabit Ethernet ports simultaneously at wire speed.

Because the Niagara-2 runs at a slightly higher clock speed with twice as many threads, but only delivers twice the throughput of Niagara-1, it would seem that going from four to eight threads per core does reduce the efficiency of the Niagara chip's threads. (My back of the envelope calculations using my trusty HP-12C show it to be a drop of 12.5 percent in thread efficiency, but only Sun really knows.) It is hard to say if goosing the clock speed further would allow Sun to get more work done, or if it would simply get the components of a Niagara system out of whack with each other, resulting in poorer performance. Keeping CPU clock speed closer to main memory clock speed has value.

The important thing is that Sun believes it can deliver a Niagara-2 chip that does about twice the work, but in the same thermal footprint as Niagara-1.

Sun is not talking about whether or not the Niagara-2 machines will be equipped with SMP or NUMA clustering, but there is plenty of talk about this. I have seen presentations from inside Sun with four Niagara chips clustered in a single system, but Sun was talking theory in these presentations, not future system specs. Sun could use the HyperTransport or JBus links to cluster machines, and we all know this. It will be interesting to see what Sun does. Clearly, there is a market for Niagara boxes with more than one processor. The question is: how many threads can operating systems and applications actually use?

As it is, the future Niagara-3 chips are expected to have more cores and therefore more threads, and are expected to use a 45 nanometer process that can allow Sun to crank the clock or cram the transistors even further, and Sun could even double the core count to 16, putting 128 threads on a single Niagara-3 chip. Obviously, putting multiple Niagara chips into a single server would produce an even higher thread count per system, perhaps 256 or 512 threads per machine. So Sun may not be inclined to go the SMP or NUMA clustering route.

Still, putting multiple Niagara chips on a single die might even make something you could call "Rock," which is the kicker to Sun's UltraSparc-IV dual-core processors that is billed as being "massively threaded." Sun has been pretty vague about what the Rock Sparc processor will be when it comes out the door in 2008, but a very beefed up architecture based on something like the Niagara chip seems to be a fair guess. It also would be interesting to see if Sun creates Rock by making a 3D multichip module out of Niagara-like chips, similar to the way IBM makes its mainframe engines out of single and now dual-core processors.

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