Intel Quietly Releases 'Montvale' Itanium Kickers

Published: November 8, 2007

by Timothy Prickett Morgan

It is hard to say why, but the launch of the "Montvale" Itanium 9100 kickers to the current dual-core "Montecito" Itanium 9000 processors could go down as the least enthusiastic launch that Intel has ever done for a microprocessor. I mean, Montvale did not even, according to Intel's PR department, rate its own set of foils last week, even though it can boost performance for customers by as much as 19 percent compared to the Montecito chips.

With Intel laying off people and restructuring, it is easy to imagine that the company is a little short-handed, which might be part of the problem. Moreover, now that the 64-bit Xeon line is fully fleshed out with quad-core processors--the "Clovertown" Xeon 6300s for two-socket machines and the "Tigerton" Xeon 7300s for four-socket and larger machines--based on the low-power Core architecture, talking about a dual-core Itanium will only beg the question of where the quad-core "Tukwila" Itaniums are. Moreover, someone might bring up the fact that two years ago, Intel was saying Montecito would be out in 2005, Montvale in 2006, and Tukwila in 2007, including a range of low-voltage parts as well as standard parts for two-socket and four-socket servers. In other words, Montvale should have already been here and gone by now, and all of Intel's chips should be quad-core at this point. And it is fair to guess that with Tukwila possibly slipping into early 2009 from its 2008 expected announcement, if the rumor mill has it right, Intel may not be in a mood to talk about any of this.

There are seven new Montvale Itanium 9100 processors, all of them implemented in a 90 nanometer process that was also used to create the Montecitos. Many people had been hoping to see Montvale have clock speeds up in the range of 2 GHz, where Montecito was designed to go, but alas, this is not going to happen and very likely because of power and cooling issues. The good news for Intel is that IBM is late with a full line of Power6 servers and Sun Microsystems won't have its "Rock" UltraSparc RK chips to market until next year.

Some Montvales have a faster 667 MHz front side bus and some have support for 533 MHz or 400 MHz buses. (Way back when, 667 MHz was originally expected to be the low-end front side bus speed for the Montecitos, were also supposed to have an 800 MHz bus according to much earlier roadmaps.) Provided a server chipset supports the faster bus speed, a Montvale chip should plug right into the same socket that a single-core "Madison" Itanium 2 or dual-core Montecito chip plugs into. Montvale chips with an M in their name have the faster bus, while those with an N have the slower bus.

All of the Montvale chips have Intel's VT hardware-assisted virtualization electronics inside of them, and the top four of the seven chips have a feature that was supposed to make it into earlier Itaniums called Demand Based Switching (DBS) built into them as well. DBS power management, which allows a CPU to burn less juice when it is inactive, has been part of the Xeon and Core chips for two years. The top five of the Itanium 9100 chips also have Intel's HyperThreading implementation of simultaneous multithreading. SMT, as this technology is abbreviated outside of Intel, allows a single core to look like two virtual cores to an operating system, sometimes allowing 20 percent to 40 percent more work to get done, depending on the instruction pipeline, the operating system, and the nature of the applications being run on the chip. Two special versions of the Montvale chips aimed at high performance computing workloads have HT and DBS deactivated and a lower price tag, which gives the Montvales a chance against Xeons, Opterons, and RISC chips such as IBM's Power5+ quad-core modules and dual-core chips as well as the new Power6 processors.

The Montvale's now bring a mainframe-class error correction technology that was in the Montecitos at the socket level, called Socket Level Lock Step, down to the core level, called Core Level Lock Step. There is no plain English explanation of exactly what this feature is as we go to press. But the press release says that it can eliminate undetected errors in a Montvale core. (Undetected by what? And if it is undetected, how can it be eliminated?)

The top-end Montvale part is the 9150M, which runs at 1.66 GHz (up from the 1.6 GHz clock speed of the Montecito) and sporting the same 24 MB L3 cache memory. It has a thermal design point (TDP of 104 watts), as do all but one Montvale chip, which has been slimmed down to 74 watts. The Itanium 9150N chip runs at a slightly slower 1.6 GHz, uses the slower 533 MHz/400 MHz bus, and has the same 104 watt thermal envelope. Both of these chips cost the same $3,692 each in 1,000-unit quantities. (All prices cited in this story will be unit prices based on buying a 1,000-unit tray of chips.) The Itanium 9140M and 9140N chips run at the same clock speeds and have the same bus speeds as these two chips mentioned above, but have only 19 MB of L3 cache and a $1,980 price tag. The Itanium 9120N steps the clock speed down to 1.42 GHz, cuts the cache back to 12 MB, deactivates the DBS feature, has the same 104 watt thermal envelope, and cuts the price in half to $910. These five chips are being aimed at traditional RISC/Unix and mainframe replacement workloads. There is no Montvale part that comes into the same $749 price point as the Montecito Itanium 9015, which was a 1.4 GHz chip with 12 MB of cache.

The 9130M and 9110N are the two chips aimed at HPC workloads. The 91130M runs at 1.66 GHz, has 8 MB of cache, a 677 MHz bus, and costs $1,552 a pop. The 9110N has the slower bus speed, runs at 1.6 GHz, has 12 MB of cache, and is the coolest (in terms of heat, mind you) of the Montvales with a 75 watt TDP. It costs $696, just like the Itanium 9010 it replaces, which also had a 75 watt TDP.

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