Intel Maps Out Its Server Roadmap

by Timothy Prickett Morgan

Brace yourself for Intel's code-name blitz for platforms, processors, chipsets, and core technology underpinning it all. Intel recently reorganized itself into five different operating groups, and the new Digital Enterprise Group, headed up by co-general managers Pat Gelsinger and Abhi Talwalker, was the star of the first day of Intel Developer Forum in San Francisco, California.

The reason this is true is that the Digital Enterprise Group is responsible for creating the PC, workstation, laptop, and server platforms that comprise the bulk of Intel's annual sales.

While Intel is certainly a diverse company, with fingers in a lot of markets, it is still largely a microprocessor company that wants to develop and integrate as many system components as it can without alienating its partner customer base. (And when the margins drop down in the electronic components business, it is not hard to imagine an Intel of the future deciding that it, rather than its partners, should be a system builder. But that is, perhaps, a story for Spring IDF 2009 or 2010.)

In the meantime, Intel has to make it easier for system builders to consume the chips, chipsets, and related technologies it is creating, and that is why Gelsinger and Talwalker have instituted a new naming scheme for technologies that talks about Intel products at the platform layer first, followed by the processors, chipsets, and other salient characteristics. Ideally, Intel wants its partners to stop buying piece parts and buy whole motherboards or subsystem boards--or, even whole servers, if that is what they really want. Secretly, this is probably Intel's deepest desire.

On the server front, Intel is getting ready to launch the "Truland" platform, which is the name of the platform that will be comprised of Intel's E8500 chipsets and the single-core "Potomac" 8MB cache and "Cranford" 1MB cache processors. The announcement of the Truland platform, which was originally expected by the end of 2004 to complete the rollout of the EM64T memory extensions to the Xeon MP server line, is expected before the end of the first quarter.

The Truland platform, like the platform based on the "Irwindale" Xeon DPs that were announced a few weeks ago, include 64-bit extensions, PCI Express I/O, DDR2 main memory, Execute Disable (XD) security, error correction on the system bus, memory, RAID, and PCI Express buses, and Demand-Based Switching (DBS) power management features.

The Irwindale Xeon DPs have 2 MB of on-chip cache. The Truland platform is expected to have a 667MHz double-pumped front side bus and will support DDR2-400 main memory.

At the end of 2005, Intel will roll out a kicker to the Truland platform that will include the "Tulsa" large cache and "Paxville" small cache dual-core 64-bit Xeon MPs, which will have two cores per processor. The company expects that systems based on these dual-core Xeon MPs will be available in the first quarter of 2006.

The Paxville chip appears to be a single-die chip, which has two Xeon MP cores on a single piece of silicon, side by side sharing a split front side bus. It is made in a 90 nanometer process. Presumably the Tulsa kicker to Paxville is also two chips on a single die, even given the large cache size on Tulsa, because Tulsa will be made in a 65 nanometer process. Tulsa may, though, come out as a multichip module with two whole Xeon chips, each with their own cache, glued together on a single piece of ceramic and fitting into a single CPU socket. Intel is not saying exactly how Tulsa will be made.

On about the same schedule--release from Intel at the end of 2005, with initial product shipments in the first quarter of 2006--Intel expects to roll out the "Bensley" Xeon DP platform. The Bensley platform will include the "Dempsey" dual-core Xeon DP--which is really two "Nocona" Xeon 1MB chips implemented in 65 nanometer chip technologies put into a single MCM that plugs into a single Xeon socket.

The Bensley platform will use a chipset codenamed "Blackford," which will come in a flavor for regular two-socket servers as well as a version called Blackford-VS for so-called "value" servers.

The Bensley platform, which Gelsinger demonstrated during his keynote last week, includes support for fully buffered DIMM memory--which increases memory bandwidth and overall system performance, particularly for multicore designs--as well as a new I/O feature called I/O Acceleration Technology (I/OAT), which speeds up the performance of TCP/IP and other CPU-related messaging technologies by making tweaks in the CPU, in the chipset, in software compilers, and in operating systems.

Intel is advancing I/OAT as a better alternative than having dedicated TCP/IP engines in a system. The Bensley platform will also be the first server to feature Virtualization Technology (VT), which is hardware-assisted virtual machine partitioning.

The Bensley platform will also sport a new technology called Active Management Technology (AMT), which is a new feature that will provide circuitry for out-of-band access to a PC or server for system administrators that can get into a machine regardless of operating system and regardless of whether the machine is activated or not so they can work on the machine.

AMT and VT are key ingredients for Intel to make PCs and servers more flexible, more secure, and easier to manage. The specs for AMT are being given to Intel partners starting last week under an NDA. Altiris, BMC Software, Check Point Software Technologies, Computer Associates, LANDesk Software, Novell, Symantec, StarSoftComm, and Trend Micro have all taken a look at the spec so they can weave their products into AMT.

Some time in the second half of 2005, Intel expects to get the dual-core "Montecito" Itanium out the door, and depending on how fast it does it and how fast vendors qualify their systems for the chip, it could end up in systems at the end of 2005 or in the beginning of 2006.

The dual-core Itaniums will be the first chips that Intel ships that sport the "Vanderpool" VT virtualization features as well as the "Pellston" error correction technology, the "Foxton" technology--which boosts the clock speed on the Itanium chip when the workload demands it and the server can take the heat; it will also include DBS power management features. Montecito is really two Madison cores, each with its own 12MB cache, jammed on a single chip but not sitting side-by-side so much as truly integrated on the die--in this regard, it is like IBM's Power4 and Power5 chips. Montecito will be made in a 90 nanometer process and will pack some 1.72 billion transistors on a die -most of it from that 24 MB of cache. A "Tiger4" Montecito system with four processors and eight threads was demonstrated last week at IDF by Gelsinger.

In 2006, Intel plans to roll out an enhanced Montecito chip called "Montvale," which will use the same E8870 chipset from Intel and which will obviously be supported by other chipsets from Hewlett-Packard, Fujitsu-Siemens, Hitachi, NEC--but not, alas, by IBM, which just got in the dog house with Intel because it has essentially and quietly discontinued its development for Itanium products.

There will also be a variant of Montecito called "Millington," which is aimed at dual-socket servers, as well as a DP variant of Montvale in 2006. Further out in 2007, Intel has committed to a server platform dubbed "Richford" that will use the multicore "Tukwila" Itanium processor--which will probably have four cores on a single die; a cut down Tukwila is expected around the same time, called "Dimona," for two-socket servers. And just to keep the Itanium naysayer at bay, Gelsinger said that beyond this, a multicore Itanium chip called "Poulson" was currently in development; this chip could hit the market in 2008 or 2009.

On the Xeon MP front, Intel also said that it would have a multicore platform called "Reidland" in the 2007 time frame, which would make use of the multicore "Whitefield" Xeon MP. Like the Tulsa Xeon MP, the Whitefield will be based on a 65 nanometer process.