AMD Sets SSE5 Spec, Brags of 'Extended' Virtualization Support
Published: September 5, 2007
by Timothy Prickett Morgan
Advanced Micro Devices and Intel continue to exchange fire in their X64 war, and last week was AMD's turn to shoot. AMD announced that it was opening up the specifications for a set of special instructions, called SSE5, to boost the performance of its future Athlon and Opteron processors. The company also said that it had hidden some electronics in its on-chip AMD-V virtualization support that allows for virtual machine hypervisors to be migrated across AMD chip generations.
AMD is, of course, making these two announcements today because Intel is planning on launching its high-end quad-core Xeon chip, code-named "Tigerton," this week in an effort to trump AMD's own quad-core "Barcelona" Opteron processor announcement the following week. They are each trying to drown the other out in the news as well as in the market for X64 processors.
The SSE5 extensions to the X64 instruction set are much more important than the virtualization announcement, and both are unquestionably less important--at least for now--than getting a competitive quad-core processor out the door to compete with Intel. Just like AMD took the bull by the horns and added 64-bit memory extensions to the X86 architecture years ahead of Intel, with the SSE5 extensions AMD is going to take the SSE instruction set developed for 32-bit X86 and 64-bit X64 processors by Intel and extend them. The SSE5 specs are also being put out there for all to see, and they include special instructions for number-crunching, media processing, and memory operations that substantially speed up the performance of applications.
SSE is Intelspeak for Streaming SIMD Extensions, and SIMD is short for Single Instruction Multiple Data. Intel introduced SSE in 1999 with its Pentium III processors, and it was a direct response to the multimedia extensions called 3DNow that AMD created for its Athlon processors. Intel has currently put forth a set of instructions called SSE4, which will appear in its future "Penryn" Core 2 processors later this year. SSE5 is a 128-bit extension to the 64-bit X64 architecture, comprised of 46 base instructions and 124 additional instructions, which will first be implemented in AMD's "Bulldozer" processor cores, slated for 2009. (The impending Barcelona Opteron processors have 128-bit floating point units, so SSE5 is not the first time 128-bit instructions are being put into the X64 architecture.)
AMD says that high performance computing, multimedia, and security applications will see big benefits from SSE5, with many orders of magnitude improvement in performance for discrete mathematical functions buried inside applications. The problem is that AMD's SSE5 is not a superset of Intel's SSE4. There is some overlap, but there is not really one set of instructions that will work in Intel and AMD chips. This will complicate software development a bit, with coders and their compilers having to pay attention to the underlying instruction set when they optimize their code.
In other news, AMD said that its single-core, dual-core, and soon quad-core Opteron and Athlon processors had a feature in their electronics that the company is now calling AMD-V Extended Migration that allows virtual machine hypervisors and their guests to migrate across generations of processors seamlessly. The most surprising thing about the AMD-V Extended Migration feature is that people were probably under the impression that there was nothing to worry about when moving virtual machines across generations of processors--everything being virtualized and all. But there are things to worry about, apparently.
AMD-V Extended Migration makes use of special registers in the AMD processors that keep track of the processor generation, the instructions that are running, and the configuration of processors; AMD-V Extended Migration allows the virtual machine hypervisor and its guests to only access features in the AMD processors that are common across the entire pool of processors. In effect, AMD-V Extended Migration ensures that VMs only use the lowest common denominator of instructions, thereby ensuring compatibility. In a language we call English, you might call this dumbing down, which is a tried-and-true means of ensuring compatibility. It has always worked for armies, navies, and educational institutions, for instance.
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Intel Sets Up 'Tigerton' Xeon MPs Against Future Opterons
AMD Sets 'Barcelona' Quad-Core Opteron Launch for August
Intel Delivers Low-Power, Quad-Core Xeon Chips
AMD: Native Quad Core Opteron Will Best Intel Quasi Quads
Intel Delivers More Quad-Core Server and PC Chips
AMD Unveils Rev F Opterons, Prepares for Quad Cores in Mid-2007
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