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Volume 4, Number 36 -- September 26, 2007

IDF Server Wrap Up: Intel to Keep the Pressure on AMD

Published: September 26, 2007

by Timothy Prickett Morgan

Chip maker Intel has finished up its fall Intel Developer Forum technical conference in San Francisco, and the company last week made it pretty clear that it is going to keep tweaking and improving its server processors and platforms at the aggressive pace that has allowed it to blunt the competitive attack from Advanced Micro Devices. AMD's quad-core "Barcelona" Opteron chips using a 65 nanometer process are just starting to ship in systems, and Intel is already gearing up improved dual-core and quad-core chips based on the "Penryn" core and a new 45 nanometer process.

Rather than try to cut off AMD's oxygen, Intel seems determined to try to outrun it and not give it time to stop and catch its breath. The end result could be the same.

Intel showed off a lot of gadgetry at IDF, as it always does, but on the server front, only two products matter. The first is the new "Penryn" Xeon processors, which will be sold as the Xeon 5400 and which will initially be available in two-socket (formerly known as Xeon DP) machines. The other is the future "Nehalem" core, which is a complete reworking of the X64 core, including on-chip memory controllers, point-to-point communications, and other features that have been differentiators (albeit in a slightly different form) for AMD's Opteron for the past several years.

Intel showed off the basic outlines of the Penryn cores back in April, when the company was also talking about how it was going to quickly ramp up its chip making to a 45 nanometer process that uses hafnium mixed with silicon to create transistors. By doping with hafnium, Intel has been able to make the next shrink in transistor size quite a bit earlier than its rivals, much as it has been a year or so ahead of its rivals with 65 nanometer technology. (IBM also figured out the hafnium trick, much as Intel learned IBM's trick of doping with copper a few years back.) By shrinking transistor sizes, as all chip makers have been doing since there were integrated circuits, vendors can add more components to the chip (such as more cores), keeping roughly the same thermal envelope. Or, they can ramp up clock speeds and give more performance per thread; drop the thermals and keep clock speeds the same or lower them (reducing performance some and thermals a lot); or employ a mix of these different approaches. As it turns out, the current lines of X64 processors from both AMD and Intel use all of these different techniques to give customers options so they can balance price, performance, and heat.

Penryn is a shrink of the current "Woodcrest" processor, which implements the Core architecture and which have been responsible for Intel's resurgence in the server chip space in the past 18 months. Paul Otellini, Intel's chief executive officer, showed off Penryn chips at the show, as did Pat Gelsinger, general manager of its Digital Enterprise Group, which makes PC and server chips as well as chipsets and platforms.

Gelsinger also showed off the next generation "Nehalem" core, the design of which was only delivered to the fab four weeks ago and is at its A0 stepping, also sometimes called first silicon. Nehalem implements a kicker to the Core architecture, and as Intel's top brass have explained many times in the past two years, their strategy is to "tick-tock" AMD into submission: A new process comes online with an established architecture, followed by a new architecture using a proven chip making process.

Intel did provide a few new details on the future Penryn class of chips, but is saving some details for later.

According to Trevor Lawless, marketing manager in Intel's Server Platforms Group, the first Penryns are for two-socket servers, and are known by the code name "Harperstown" and "Wolfdale," with the related platform being known as "Stoakley." Harperstown is a four-core chip (two dual-core chips in a single package) while Wolfdale, expected before the end of the year, is a dual-core variant (one dual-core chip in a package).

The Penryn cores will have new SSE4 instructions aimed at improving performance on specific functions related to number crunching, media processing, and so on, and the chips will also have a maximum of 6 MB of on-chip, shared L3 cache for each dual-core chip, to the 2 MB of dedicated L3 cache per core for the Woodcrest processors. The Harperstown and Wolfdale chips will also have a 1.6 GHz front side bus, which is faster than the current 1.3 GHz bus. However, the kicker is that the Stoakley platform that also knows how to use this faster front side bus is being aimed at workstation and high-performance computing (HPC) workloads, not at general-purpose servers. According to Lawless, server makers want to continue using the current "Bensley" server platform for two-socket servers, which use dual-core Woodcrest Xeon 5100 and quad-core "Clovertown" Xeon 5300 chips, until the Nehalems arrive. Server makers are working with Intel on designs for the Nehalem chips due in the second half of next year--which have a significantly different architecture and therefore take much more time to qualify--and the lifespan of a Stoakley server platform would be too short to be worth their while. Presumably Intel will have Harperstown and Wolfdale chips with slower bus speeds for the Bensley server platforms.

Intel has not divulged what specific speeds the Penryn chips used in servers will run at, nor has it talked pricing. This will be done at the November 12 launch. The company has said that Harperstown chips will run at 3 GHz and above, and will have better thermals than the Clovertowns. The dual-core Penryn Xeons will come with thermal design points (TDPs) of 40 watts, 65 watts, and 80 watts, while the quad-core versions of the Xeons will have 50 watt, 80 watt, and 120 watt TDPs. Lawless says that the performance boost will be anywhere from 7 percent to 20 percent, depending on the workload, but for a given clock speed, the 45 nanometer shrink will dramatically lower the thermals, offering much better performance per watt.

On the stage at IDF, Gelsinger demonstrated two quad-core, eight-thread Nehalem processors linked together with the future QuickPath Interconnect (QPI) point-to-point links working, which is a remarkable achievement. Intel certainly did not move this quickly from idea to silicon in the past. Nehalem has simultaneous multithreading (which AMD does not offer) as well as an on-chip main memory controller and on-chip interconnection, which AMD has done from the get-go with Opterons and their HyperTransport interconnect. With the Nehalem, not only is Intel putting in a new core, it is ditching the front side bus architecture. (Something it should have done years ago but could not do easily.)

Gelsinger says that the future "Westmere" kicker to Nehalem, which is being designed in Oregon and uses a 32 nanometer process, is under way and due in 2009, on schedule. In 2010, by a tweaked architecture code-named "Gesher," also to be implemented in 32 nanometer processes, will also come out.

"The tick-tock engine doesn't pause," Gelsinger said during his keynote at IDF. "It delivers predictable, powerful, efficient performance for the industry, for Intel, and ultimately for our customers."

Which makes you wonder how AMD ever got a foothold in servers to begin with. It is safe to say that Intel's clock was wound down a bit by its desire to pump up Itanium, but it sure has been wound back up now.


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