Intel Pushes Out Dual-Core Itaniums, Or Does It?

by Timothy Prickett Morgan

To hear the top brass at Intel talk about it, everything is fine and dandy in Itanium land, and the fact that the dual-core "Montecito" Itanium processors have been pushed out to a volume ramp up in the first half of 2006 is not only not a problem, it has apparently been the plan all along. This will, of course, come as something of a surprise to the server makers who are dependent on the Itanium roadmap to plan their product rollouts.

Server makers know a thing or two about ramps, just like Evil Knievel, who famously jumped 13, then 19, then 50 cars on his motorcycle in the 1970s. "There were a couple of ramps I wish I had hit a bit faster," he once explained. "But apart from that, I have had a good life." He also explained that fear was part of the deal. "People said I wasn't scared before a jump. I was scared. I'd have a shot of Wild Turkey before each jump to calm myself." If Evil needed a shot as he hit the ramp, server makers who have embraced the Itanium in the past several years probably needed to have a few shots, because unlike the beginning and ending ramps that gave Evil the speed to make his jumps and then land safely on the other side, Intel has quite a few times changed the Itanium ramps on them. It's hard to make the jump when the ramps are moving.

In a conference call last week with members of the press and analyst community at the debut of the new large cache "Madison" generation of Itaniums, Abhi Talwalker, vice president and general manager of Intel's Enterprise Platforms Group, said that the fact that the Montecito Itaniums were now slated for delivery to end user customers in the second half of 2006 as not a delay. "I don't see it as a slip," he said. "You guys all know that this class of systems takes time to certify." He said that Intel was "making great progress with the silicon" on Montecito, referring to the new 90 nanometer process technology that will allow Intel to cram two Itanium cores and 24 MB of L3 cache memory onto the die, another 33 percent more than Intel just launched this week with the tweaked "Madison" chips, which have 9 MB of L3 cache on chip. He said that Intel had shipped samples of the Montecito chips to server makers Talwalker also reminded everyone that these dual-core chips would plug into any Madison socket, protecting customer investments, and added that the company was focused on getting trials of the new chip started in the third quarter of 2005 or early in the fourth quarter, with volume shipment in the first half of 2006. The first half of 2006 is a big ramp to try to land on, having 26 weeks in it, and you can bet that Intel knows this. When pressed about whether or not this timing represented a delay, Talwalker said that "this was always the plan from a volume standpoint."

If the server makers aren't surprised by such a statement, the IT community that reads the IT press certainly is. In the 2002 server chip roadmaps, Montecito was the code-name for the single-core Itanium that would be the first processor to use the 90 nanometer process and which would be available in 2004. Back then, Intel had not planned to bring out dual-core Itanium processors until 2006, with the "Chivano" Itaniums. In January 2003, when Intel was revamping its server chip roadmaps, as it often does, Intel killed off the Chivano chips, pushed out Montecito into 2005, but made it a dual-core chip. So the Montecito features (like Pellston Technology for correcting cache line errors, Silvervale Technology for hardware-assisted virtualization, Foxton Technology for briefly turbocharging performance, and demand-based switching for better power management) were being pushed out a bit, but Intel was moving forward dual-core chips in response to competitive pressure from AMD and RISC/Unix players.

The Madison 9 MB chip came to market in the first place to plug a gap created when the single-core Montecito chip was pushed out, but the surprising thing about Intel is that this Madison 9MB chip seems to be the only thing Intel is going to offer in the Itanium space between now and when Montecito is available. That could be anywhere from 12 to 18 months from now. That is a long, long time in the server business, especially when other chip makers are going to be boosting performance by adding cores and cranking clocks. Moreover, with an expected 1.5 to 2 times the performance of the new Madison 9 MB chip, it seems that Intel will not be able to crank up the clock speeds very much on the Montecito chip and that the bulk of the performance gain will come from simply having two cores on the die. (This is true of many dual core processors, which allow vendors to keep clocks constant, but shrink circuits and double up on core count in the same heat profile.) From the outside, it looks like Intel is constrained as much by the 130 watt heat dissipation envelope for the top-end Itanium as it is by the yields on its current 130 nanometer and future 90 nanometer processes.