IBM Readies October Power Systems Announcements

October 10, 2011 Timothy Prickett Morgan

The word on the street is that IBM is gearing up for some new Power Systems announcements. The exact nature of the announcements is not clear, but I am hearing a little bit of this and a little bit of that about what Big Blue has cooking for its IBM i, AIX, and Linux customers who use Power-based systems. What I can tell you for sure that whatever Big Blue is up to, and contrary to what some of its own roadmaps have been pointing to, it is not calling it the Power7+ server refresh.

I don’t yet know if that means there is not going to be a Power7+ processor refresh or if IBM is going to try to pretend there wasn’t one, which was the case with the Power6+ processor launch in October 2008. Remember that, when IBM doubled up the core count on a bunch of midrange Power Systems iron? And it wasn’t until April 2009 that I figured out that these machines were actually based on Power6+ chips, which had some minor tweaks instead of the revamp in transistor technology and higher frequencies that IBM had planned in its 2005 and 2006 Power roadmaps. That latter 2006 roadmap promised higher frequencies and “multi-core” compared to the dual-core, 4 GHz Power6 chips.

Some of the roadmaps I have seen clearly have a Power7+ revamp at the end of 2011, and software roadmaps made reference to it as well, as I have shown in multiple issues of this newsletter. And I have been writing planning stories based on the idea that it was coming, not just because of these roadmaps but because I heard rumblings about future Power Systems machines coming out. Rumblings are never precise, of course.

Just like the ones I heard late last week, when IBM started prebriefing business partners on the October Power Systems announcements. What I heard for sure is that whatever is coming down, IBM is not calling it a Power7+ launch. Maybe instead of launch a new chip based on a new 32 nanometer process, which I showed you back in August, IBM is going to do a deep bin sort on the Power7 chips and find a few that run at higher clock speeds. Every other server chip maker does this. In fact, Intel and Advanced Micro Devices both did it at the beginning of the year with their respective six-core Xeon 5600 and twelve-core Opteron 6100 processors.

Moreover, with Intel not launching its eight-core Xeon E5 processors until sometime early next year and the rumor last week that AMD is perhaps mirroring that move instead of trying to launch any week now, Big Blue might not be feeling enough pressure to get the Power7+ out the door. IBM is certainly not feeling any pressure from Itanium-based systems, not with Oracle yanking support on future “Poulson” Itaniums, due next year, and Hewlett-Packard bringing in yet another CEO, Meg Whitman, with what will probably be yet another turnaround plan. The new Sparc T4 processors from Oracle will give IBM a run for the money, but the Power7 chips can compete with them, particularly if IBM gooses memory capacity on Power Systems.

All I know for sure is that I report what I find out as I find it out and try to make sense of it. It is an imperfect process, not the least of which because vendors keep changing what they are doing and they hardly talk publicly about what they are doing any more because commitments are odious, apparently. (I find Oracle quite refreshing in that it has shared public roadmaps to try to regain some credibility that Sun lost over the past decade of chip delays and failures.)

What I can tell you is that people familiar with IBM’s plans say that the Power Systems line is going to be enhanced in some manner across their processors, memory, and storage. The entry Power 720 and 740 systems are getting fatter memory capacity and so are the enterprise-scale Power 770 and Power 780. IBM is also apparently goosing the PCI-Express peripheral bus to the 2.0 level, and I have to be honest with you, I thought this had already happened in April 2009. IBM is moving to PCI-Express 2.0 just as Intel is getting ready to launch PCI-Express 3.0 on the Xeon E5 processors–and with dual PCI-Express 3.0 controllers right on the chip, at that.

Let me say this: If IBM doesn’t have Power7+ and PCI-Express 3.0 technologies in the hopper for launch in 2012, it is sure gonna wish it had. Of course, there is no hot technology that can’t be undone by a good discount on an existing technology. And for the workloads IBM is targeting with the Power Systems machines–back-end database and application serving–having multiple network and disk controllers hanging off the system is no big deal. That integrated PCI-Express 3.0 controller on the chip is really going to shine on hyperscale cluster and supercomputer applications, though–particularly those that use out-board GPU co-processors to do a lot of the floating point calculations.

It is also not clear when these announcements will take place. It could happen this week, which would be a weird time given the Columbus Day holiday in the United States, or it could happen the week after that. Whatever it is, we’ll keep you appraised of the situation as soon as we know. Stay tuned.