Volume 15, Number 9 -- February 27, 2006

IBM Research Pushes Chip Tech Down Below 30 Nanometers

Published: February 27, 2006

by Timothy Prickett Morgan

IBM's Almaden Research Center in San Jose, California, and development partner JSR Micro, a Sunnyvale, California, maker of the components that go into chips, announced last week that they have pushed the photolithography methods used to make chips beyond the 32-nanometer limit that the chip industry has expected photolithography to peter out at.

SPIE Microlithography 2006 conference being held in San Jose, IBM and JSR showed off some circuits they had created using a technique called immersion photolithography that could draw circuits with line widths at 29.9 nanometers, one-third the size of the current 90 nanometer circuits commonly made today and less than half the size of the top-end 65 nanometer circuits that are just starting to come online.

With immersion photolithography, the laser light beams that are used to etch circuits into photosensitive material on silicon wafers are focused by a layer of water that surrounds the wafer. Because light slows down when it enters the water, you can crank the light up to a higher frequency, which yields a tighter laser beam, and therefore the ability to etch smaller circuits. Using a technique nicknamed Nemo, IBM and JSR have used a twist on the immersion technique that has two laser beams operating at slightly different frequencies that etch indirectly using an interference pattern created by the two beams. IBM and JSR think they can push Nemo even further by jacking up the refractive index of the fluid and lenses used to focus the laser beams.

What the industry doesn't want to do is move to other techniques, such as extreme ultraviolet lithography (which is actually using x-rays) because such a switch will be very expensive and the technology, unlike photolithography, is completed untested in production environments. Just think about it this way. Each time you cut the size of the circuits in half, you can quadruple the performance of the chip because now you can quadruple the number of components on the chip or you can keep the same components and run them four times faster. So moving from the 90 nanometer circuits of the Power5+ chips from early 2006 to something on the order of 30 nanometers should result in Power chips that have nearly nine times the performance.

That's if this Nemo process can be commercialized and it wins out against other methods.

"Our goal is to push optical lithography as far as we can so the industry does not have to move to any expensive alternatives until absolutely necessary," says Robert Allen, manager of lithography materials at the Almaden Research Center. "This result is the strongest evidence to date that the industry may have at least seven years of breathing room before any radical changes in chip-making techniques would be needed."

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Editor: Timothy Prickett Morgan
Contributing Editors: Dan Burger, Joe Hertvik, Shannon O'Donnell,
Mary Lou Roberts, Victor Rozek, Kevin Vandever, Hesh Wiener, Alex Woodie
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